Designing circuits with partial scan

IEEE Design and Test of Computers

Volumn 5, Issue 2, 1988, Pages 8-15

  Agrawal, Vishwani D ^a   Lin, Tonysheng ^a   Cheng, Kwang Ting ^b   Johnson, Daniel D ^c  

^a LUCENT TECHNOLOGIES   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c NONE

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRONIC CIRCUITS, FLIP FLOP; FAILURE ANALYSIS -- ESTIMATION; INTEGRATED CIRCUIT TESTING; LOGIC DESIGN -- TESTING;

FLIP-FLOPS SELECTION; FUNCTIONAL TESTABILITY; PARTIAL SCAN;

INTEGRATED CIRCUITS, VLSI;

EID: 0023985656     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/54.2032     Document Type: Article

References (8)

1. V.D. Agrawal, S.K. Jain, and D.M. Singer, “Automation in Design for Testability”, Proc. Custom Integrated Circuits Conf., May 1984, pp. 159–163.
2. V.D. Agrawal, “Synchronous Path Analysis in MOS Circuit Simulator”, Proc. Design Automation Conf., June 1982, pp. 629-635.
3. M.R. Mercer, V.D. Agrawal, and C.M. Roman, “Test Generation for Highly Sequential Scan-Testable Circuits Through Logic Transformation”, Proc. Int'l Test Conf., Oct. 1981, pp. 561-565.
4. E. Trischler, “Incomplete Scan Path with an Automatic Test Generation Methodology”, Proc. Int'l Test Conf., Nov. 1980, pp. 153-162.
5. P. Goel, “An Implicit Enumeration Algorithm To Generate Tests for Combinational Logic Circuits”, IEEE Trans. Computers, Mar. 1981, pp. 215-222.
6. R.K. Brayton et al., Logic Minimization Algorithms for VLSI Synthesis, Kluwer Academic Publishers, Boston, 1984.
7. T. Lin and V.D. Agrawal, “A Test Generator for Scan-Design VLSI Circuits”, Proc. AT&T Conf. Electronic Testing, Oct. 1986, pp. 23.1-23.7.
8. V.D. Agrawal, “Sampling Techniques for Determining Fault Coverage in LSI Circuits”, J. Digital Systems, 1981, pp. 189–202.