Finite element analysis of stress distributions in interconnect structures

European Solid-State Device Research Conference

Volumn , Issue , 1997, Pages 452-455

  Coughlan, J ^a   Foley, S ^a   Mathewson, A ^a  

^a UNIVERSITY COLLEGE CORK   (Ireland)

Author keywords

[No Author keywords available]

Indexed keywords

DIELECTRIC MATERIALS; STRESSES;

DELAMINATION FAILURE; INTER-METAL DIELECTRICS; INTERCONNECT STRUCTURES; INTERCONNECT SYSTEMS; METAL INTERFACE; STRESS GRADIENT;

FINITE ELEMENT METHOD;

EID: 0008457214     PISSN: 19308876     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDERC.1997.194463     Document Type: Conference Paper

References (7)

1. S.Foley, A.Ryan, D.Martin and A.Mathewson, A Study of the Influence of Inter-Metal Dielectrics on Electromigration Performance, in Proc. ESREF conf., 1995, pp.181-187
2. H.Shibata, T.Matsumo and K.Hashimoto, Via-hole related simultaneous stress-induced extrusion and void formation in Al interconnects, in Proc. IEEE IRPS conf., 1993, pp. 340-344
3. J.A.Walls, Stress-Voiding in Tungsten-Plug Interconnect Systems by High-Temperature Processing, in IEEE Electron Device Letters, Vol. 16 No. 10, October 1995
4. Y.-H.Lee, K.Wu, N.Mielke, L.J.Ma and S.Hui, Via Delamination-A Novel Electromigration Failure Mechanism, in Proc. IEEE IRPS conf., 1997
5. Swanson Analysis Systems, Inc., P.O. Box 65, Johnson Road, Houston, PA 15342-0065, ANSYS Users Manual.
6. J.Lee, Q.Ma, T.Marieb, A.S.Mack, H.Fujimoto, P.Flinn, B.Woolery and L.Keys, Measurement and Modelling of Intrinsic Stresses in CVD W Lines, in Proc. MRS Symposium, Vol.391, pp 115-119, 1995.
7. D.Butler, Options for multilevel metallization, in Solid State Technology, Vol. 39, No. 3, March 1996.