Array data flow analysis for load-store optimizations in fine-grain architectures 1

International Journal of Parallel Programming

Volumn 24, Issue 6, 1996, Pages 481-512

  Bodîk, Rastislav ^a   Gupta, Rajiv ^a  

^a University of Pittsburgh ^*  (United States)

Author keywords

Data dependence analysis; Data flow analysis; Load store optimizations; Partial dead code elimination; Partial redundancy elimination

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; OPTIMIZATION; PARALLEL PROCESSING SYSTEMS; REDUNDANCY;

ARRAY LOAD STORE OPTIMIZATION; DATA DEPENDENCE ANALYSIS; DATA FLOW ANALYSIS; FINE GRAIN ARCHITECTURES; MULTIPLE LOOP ITERATIONS; PARTIAL DEAD CODE ELIMINATION; PARTIAL REDUNDANCY ELIMINATION; REGISTER TO REGISTER SHIFT OPERATIONS;

STORAGE ALLOCATION (COMPUTER);

EID: 0030380815     PISSN: 08857458     EISSN: None     Source Type: Journal    
DOI: 10.1007/BF03356757     Document Type: Article

References (21)

1. Alfred V. Aho, Ravi Sethi, and Jeffrey D. Ullman, Compilers, Principles, Techniques, and Tools, Addison-Wesley, 1986.
2. M. E. Benitez and J. W. Davidson, Code Generation for Streaming: an Access/Execute Mechanism, Proc. of Arch. Support for Programming Languages and Operating Sysicms-IV, pp. 132-141 (1991).
3. D. Callahan, S. Carr, and K. Kennedy, Improving Register Allocation for Subscripted Variables, Proc. of the SIGPLAN Conf. on PLD1, White Plains, New York, pp. 53-65 (June 1990).
4. S. Carr and K. Kennedy, Scalar Replacement in the Presence of Conditional Control Flow, Software-Practice ami Experience, 24(l):51-77 (January 1994).
5. E. Duestenvald, R. Gupta, and M. L. Sofia, Register Pipelining: An Integrated Approach to Register Allocation for Scalar and Subscripted Variables, Proc. of Infl. Workshop on Compiler Construction, LNCS 641 Springer Verlag, Paderborn, Germany, pp. 192-206 (October 1992).
6. E. Duesterwald, R. Gupta, and M. L. Sofia, A Practical Data Flow Framework for Array Reference Analysis and its Application in Optimizations, Proc. of ACM SIGPLAN Conf. PLD1, Albuquerque, New Mexico, pp. 68-77 (June 1993).
7. D. M. Dhamdhere, Practical Adaption of the Global Optimization Algorithm of Morel and Renvoise, ACM Trans, on Programming Languages ana" Systems, 13(2):291-294 (April 1991).
8. D. M. Dhamdhere, B. K. Rosen and F. K. Zadeck, How to Analyze Large Programs Efficiently and Informatively, Proc. of the SIGPLAN PLDI, San Francisco, California, pp. 212-223 (June 1992).
9. J. Knoop, O. Ruthing, and B. Stefien, Optimal Code Motion: Theory and Practice, ACM TOPLAS, 16(4): 1117-1155.
10. E. Morel and C. Renvoise, Global Optimization by Suppression of Partial Redundancies, Comm. ACM, 22 (2): 96-103 (1979).
11. M. Wolfe and U. Banerjce, Data Dependence and its Application to Parallel Processing, UPP, 16 (2): (April 1987).
12. L. Hendren, G. R. Gao, E. R. Altman, and C. Mukerji, A Register Allocation Framework Based Upon Hierarchical Cyclic Interval Graphs, Infl. Workshop on Compiler Construction, LNCS 641 Springer Verlag, Germany, pp. 176-191 (1992)
13. R. Gupta, Generalized Dominators and Post-Dominators, The 19th Ann. ACM SIGPLAN-SIGACT Symp. on Principles of Programming Languages, Albuquerque, New Mexico, pp. 246-257 (January 1992).
14. T. H. Cormen, C. E. Leiserson, and R. L. Rivest, Introduction to Algorithms, The MIT Press, Cambridge, Massachusetts (1990).
15. B. R. Ran. M. Lee, P. P. Tirumalai, M. S. Schlansker, Register Allocation for Software Pipelined Loops, Proc. of the SIGPLAN Conf. PLDI, San Francisco, California, pp. 212-223 (June 1992).
16. J. C. Dehne, P. Y.-T. Hsu, and J. P. Bratt, Overlapped Loop Support in the Cydra 5, Proc. of ASPLOS-III, pp. 26-39 (1989).
17. P. Kolte and M. J. Harrold, Load/Store Range Analysis for Global Register Allocation, Proc. of the SIGPLAN Conf. PLDI, Albequerque, New Mexico, pp. 268-277 (June 1994).
18. V. Kathail, M. Schlansker, and B. Rau, HPL PlayDoh Architecture Specification: Version 1.0, H PL-93-80 (February 1994).
19. B. R. Rau, Data Flow and Dependence Analysis for Instruction-Level Parallelism, Fourth Annual Workshop on Languages and Compilers for Parallel Computing, Santa Clara, California (August 1991).
20. R. Bodik and R. Gupta, Optimal Placement of Load-Store Operations for Array Accesses in Loops, Technical Report 95-03, DCS, University of Pittsburgh (1995).
21. G. J. Chaitin, Register Allocation and Spilling via Graph Coloring, Proc. of the SIGPLAN Symp. on Compiler Construction, SIGPLAN Notices, 17(6):98-105 (June 1982).