Array data flow analysis for load-store optimizations in fine-grain architectures 1

International Journal of Parallel Programming

Volumn 24, Issue 6, 1996, Pages 481-512

  Bodîk, Rastislav ^a   Gupta, Rajiv ^a  

^a Learning Research and Development Ctr   (United States)

Author keywords

Data dependence analysis; Data flow analysis; Load store optimizations; Partial dead code elimination; Partial redundancy elimination

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; OPTIMIZATION; PARALLEL PROCESSING SYSTEMS; REDUNDANCY;

ARRAY LOAD STORE OPTIMIZATION; DATA DEPENDENCE ANALYSIS; DATA FLOW ANALYSIS; FINE GRAIN ARCHITECTURES; MULTIPLE LOOP ITERATIONS; PARTIAL DEAD CODE ELIMINATION; PARTIAL REDUNDANCY ELIMINATION; REGISTER TO REGISTER SHIFT OPERATIONS;

STORAGE ALLOCATION (COMPUTER);

EID: 0030380815     PISSN: 08857458     EISSN: None     Source Type: Journal    
DOI: 10.1007/BF03356757     Document Type: Article

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