Numerical investigation for a grounded gate NMOS transistor under electrostatic discharge (ESD) through TLP method

Microelectronics Reliability

Volumn 40, Issue 8-10, 2000, Pages 1473-1477

  Galy, P ^a   Berland, V ^a   Foucher, B ^b   Lombaert Valot, I ^b   Guilhaume, A ^c   Chante, J P ^c   Dufrenne, S ^d   Bardy, S ^d  

^a PÔLE UNIVERSITAIRE LÉONARD DE VINCI   (France)

^b Cent Commun de Recherches   (France)

^c UNIVERSITÉ DE LYON   (France)

^d NXP SEMICONDUCTORS   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 0003318267     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0026-2714(00)00161-X     Document Type: Article

References (6)

1. T. Maloney and N. Khurana, "Transmission line pulsing techniques for circuit modeling of ESD Phenomena ", EOS/ESD Symposium Proceedings, 1985, pp 49-54.
2. G. Notermans, P. de Jong and F. Kuper, "Pitfalls when correlating TLP, HBM and MM testing", EOS/ESD Symposium Proceedings, 1998.
3. A. Amerasekera, C. Duvvury, "ESD in Silicon Integrated Circuits", John Wiley & Sons, New York, 1995.
4. SZE, S.M., "Physics of semiconductor devices", Wiley Ed., 2nd Ed, 1981, pp442-456.
5. Avanti Davinci, User's manual version 4.1, 1998.
6. G. Notermans et al. "The effect of suicide on ESD performance", 37 th Annual International Reliability Physics Symposium, IRPS 1999.