Smart and Fast:Test Generation for VLSI Scan-Design Circuits

IEEE Design and Test of Computers

Volumn 3, Issue 4, 1986, Pages 43-54

  Abramovici, M ^a   Kulikowski, J J ^a   Menon, P R ^a   Miller, D T ^a  

^a AT & T Information systems ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 0002551468     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.1986.294975     Document Type: Article

References (20)

1. P. Goel and B.C. Rosales, “PODEM-X: An Automatic Test Generation System for VLSI Logic Structures,” Proc. 18th De-sign Automation Conf., June 1981, pp. 260–268.
2. C. Radke, “Experiences in VLSI Testing,” IEEE Design and Test ofComputers, Vol. 3, No. 1, Feb. 1986, pp. 83–85.
3. M. Abramovici, P.R. Menon and D.T. Mil-ler, “Critical Path Tracing: An Alternative to Fault Simulation,” IEEE Design and Test of Computers, Vol. 1, No. 1, Feb. 1984, pp. 83–93.
4. E.B. Eichelberger and T.W. Williams, “A Logic Design Structure for LSI Testabili-ty,” Proc. 14th Design Automation Conf, June 1977, pp. 462–468.
5. S. Funatsu, N. Wakatsuki, and T. Arima, “Test Generation Systems in Japan,” Proc. 12th Design Automation Conf, June 1975, pp. 114–122.
6. M. Abramovici et al., “Test Generation in LAMP2: System Overview,” Proc. 1985 Int'l Test Conf., Nov. 1985, pp. 45–48.
7. T. Ogihara et al., “Test Generation for Scan Design Circuits with Tri-State Mod-ules and Bidirectional Terminals,” Proc. 20th Design Automation Conf, Conf, June 1983, 71–78.
8. P. Goel and B.C. Rosales, “Test Generation and Dynamic Compaction of Tests,” Proc. 1979 Test Conf, Oct. 1979, pp. 189–192.
9. P. Goel, “RAPS Test Pattern Generator,” IBM Technical Disclosure Bulletin, Vol. 21, No. 7, Dec. 1978, pp. 2787–2791.
10. A. Yamada et al., “Automatic System Lev-el Test Generation and Fault Location for Large Digital Systems,” Proc. 15th Design Automation Conf, June 1978, pp. 347–352. 352.
11. M. Abramovici, RR. Menon, and D.T. Miller, “Checkpoint Faults are not Suffi-cient Target Faults for Test Generation,” IEEE Trans. Computers, Vol. C-35, No. 8, Aug. 1986, pp.769-771.
12. P. Goel, “An Implicit Enumeration Algo-rithm to Generate Tests for Combinational Logic Circuits,” IEEE Trans. Computers, Vol. C-30, No. 3, Mar. 215–222.
13. H. Fujiwara and T. Shimono, “On the Ac-celeration of Test Generation Algorithms,” IEEE Trans. Computers, Vol. C-32, No. 12, Dec. 1983, 1137–1144.
14. L.H. Goldstein, “Controllability/Observa-bility Analysis of Digital Circuits,” IEEE Trans. Circuits and Systems, Vol. CAS-26, 26, No. 9, Sept. 1979, pp. 685–693.
15. J. Savir, “Good Controllability and Obser-vability Do Not Guarantee Good Testabili-ty,” IEEE Trans. Computers, Vol. C-32, No. 12, Dec. 1983, pp. 1198–1200.
16. G.R. Putzolu and J.P. Roth, “A Heuristic Algorithm for the Testing of Asynchronous Circuits,” IEEE Trans. Computers, Vol. C-20, No. 6, June 1971, pp. 639–647.
17. R.A. Rutman, “Fault Detection Test Gen-eration for Sequential Logic by Heuristic Tree Search,” IEEE Computer Group Re-pository, paper no. R-72-187, 1972.
18. P. Goel and B.C. Rosales, “Dynamic Test Compaction with Fault Selection Using Sensitizable Path Tracing,” IBM Techni-cal Disclosure Bulletin, Vol. 23, No. 5, Oct.
19. E Brglez, P. Pownall, and P. Hum, “Accel-erated ATPG and Fault Grading via Test-ability Analysis,” Proc. 1985 IEEE Int'l. Symp. Circuits and Systems, June 1985.
20. Special session on “Recent Algorithms for Gate-Level ATPG with Fault Simulation and Their Performance Assessment,” Proc. 1985 IEEE Int'l Symp. Circuits and Systems, June 1985