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Volumn 3, Issue 3, 1992, Pages 350-363

On Time Mapping of Uniform Dependence Algorithms into Lower Dimensional Processor Arrays

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EID: 0002140529     PISSN: 10459219     EISSN: None     Source Type: Journal    
DOI: 10.1109/71.139208     Document Type: Article
Times cited : (53)

References (37)
  • 1
    • 0001512318 scopus 로고
    • The organization of computations for uniform recurrence equations
    • July
    • R. M. Karp, R.E. Miller, and S. Winograd, “The organization of computations for uniform recurrence equations,” J. ACM, vol. 14, no. 3, pp. 563–590, July 1967.
    • (1967) J. ACM , vol.14 , Issue.3 , pp. 563-590
    • Karp, R.M.1    Miller, R.E.2    Winograd, S.3
  • 2
    • 0022482205 scopus 로고
    • Partitioning and mapping algorithms into fixed size systolic arrays
    • Jan.
    • D.I. Moldovan and J. A. B. Fortes, “Partitioning and mapping algorithms into fixed size systolic arrays,” IEEE Trans. Comput., vol. C-35, pp. 1–12, Jan. 1986
    • (1986) IEEE Trans. Comput. , vol.C-35 , pp. 1-12
    • Moldovan, D.I.1    Fortes, J.A.B.2
  • 4
    • 0021230692 scopus 로고
    • Automatic synthesis of systolic arrays from uniform recurrent equations
    • P. Quinton, “Automatic synthesis of systolic arrays from uniform recurrent equations,” in Proc. 11th Annu. Symp. Comput. Architecture, 1984, pp. 208–214.
    • (1984) Proc. 11th Annu. Symp. Comput. Architecture , pp. 208-214
    • Quinton, P.1
  • 5
    • 0003496098 scopus 로고
    • Regular iterative algorithms and their implementations on processor arrays
    • Stanford Univ, Stanford, CA, Oct.
    • S. K. Rao, “Regular iterative algorithms and their implementations on processor arrays,” Ph.D. dissertation, Stanford Univ., Stanford, CA, Oct. 1985.
    • (1985) Ph.D. dissertation
    • Rao, S.K.1
  • 6
    • 38249041270 scopus 로고
    • A design methodology for synthesizing parallel algorithms and architectures
    • Dec.
    • M. Chen, “A design methodology for synthesizing parallel algorithms and architectures,” J. Parallel Distributed Comput., Dec. 1986, pp. 461–491.
    • (1986) J. Parallel Distributed Comput. , pp. 461-491
    • Chen, M.1
  • 7
    • 0039125086 scopus 로고
    • An illustration of a methodology for the construction of efficient systolic architectures in VLSI
    • J.-M. Delosme and I.C.F. Ipsen, “An illustration of a methodology for the construction of efficient systolic architectures in VLSI,” in Proc. Second Int. Symp. VLSI Technol., Syst. Appl., 1985, pp. 268–273.
    • (1985) Proc. Second Int. Symp. VLSI Technol., Syst. Appl. , pp. 268-273
    • Delosme, J.-M.1    Ipsen, I.C.F.2
  • 8
    • 0003859414 scopus 로고    scopus 로고
    • VLSI Array Processors
    • Englewood Cliffs, NJ: Prentice-Hall
    • S. Y. Kung, VLSI Array Processors. Englewood Cliffs, NJ: Prentice-Hall, 1987.
    • Kung, S.Y.1
  • 10
    • 0021784324 scopus 로고
    • The design of optimal systolic arrays
    • Jan.
    • G.-J. Li and B. W. Wah, “The design of optimal systolic arrays,” IEEE Trans. Comput., vol. C-34, pp. 66–77, Jan. 1985.
    • (1985) IEEE Trans. Comput. , vol.C-34 , pp. 66-77
    • Li, G.-J.1    Wah, B.W.2
  • 11
    • 0022874054 scopus 로고    scopus 로고
    • A comparative study of two systematic design methodologies for systolic arrays
    • M. T. O’Keefe and J. A. B. Fortes, “A comparative study of two systematic design methodologies for systolic arrays,” in Proc. 1986 Int. Conf. Parallel Processing, pp. 672–675.
    • Proc. 1986 Int. Conf. Parallel Processing , pp. 672-675
    • O’Keefe, M.T.1    Fortes, J.A.B.2
  • 13
    • 0016026944 scopus 로고
    • The parallel execution of DO loops
    • Feb.
    • L. Lamport, “The parallel execution of DO loops,” Commun. ACM, vol. 17, no. 2, pp. 83–93, Feb. 1974.
    • (1974) Commun. ACM , vol.17 , Issue.2 , pp. 83-93
    • Lamport, L.1
  • 14
    • 0023578206 scopus 로고    scopus 로고
    • Minimum distance: A method for partitioning recurrences for multiprocessors
    • J.-K. Peir and R. Cytron, “Minimum distance: A method for partitioning recurrences for multiprocessors,” in Proc. 1987 Int. Conf Parallel Processing, pp. 217–225.
    • Proc. 1987 Int. Conf Parallel Processing , pp. 217-225
    • Peir, J.-K.1    Cytron, R.2
  • 15
    • 51249174303 scopus 로고
    • Subspace scheduling and parallel implementation of non-systolic regular iterative algorithms
    • V. P. Roychowdhury and T. Kailath, “Subspace scheduling and parallel implementation of non-systolic regular iterative algorithms,” J. VLSI Signal Processing, vol. 1, 1989.
    • (1989) J. VLSI Signal Processing , vol.1
    • Roychowdhury, V.P.1    Kailath, T.2
  • 16
    • 0026171591 scopus 로고
    • Time optimal linear schedules for algorithms with uniform dependencies
    • June
    • W. Shang and J.A.B. Fortes, “Time optimal linear schedules for algorithms with uniform dependencies,” IEEE Trans. Comput., vol. 40, pp. 723–742, June 1991.
    • (1991) IEEE Trans. Comput. , vol.40 , pp. 723-742
    • Shang, W.1    Fortes, J.A.B.2
  • 17
    • 0023347279 scopus 로고
    • Optimal systolic design for the transitive closure and the shortest path problems
    • May
    • S.Y. Kung, S. C. Lo, and P. S. Lewis, “Optimal systolic design for the transitive closure and the shortest path problems,” IEEE Trans. Comput., vol. C-36, pp. 603–614, May 1987.
    • (1987) IEEE Trans. Comput. , vol.C-36 , pp. 603-614
    • Kung, S.Y.1    Lo, S.C.2    Lewis, P.S.3
  • 18
    • 0003449348 scopus 로고    scopus 로고
    • Linear Algebra and its Applications
    • second ed. New York: Academic
    • G. Strang, Linear Algebra and its Applications, second ed. New York: Academic, 1980.
    • Strang, G.1
  • 19
    • 0022893044 scopus 로고    scopus 로고
    • Doacross: Beyond vectorization for multiprocessors (extended abstract)
    • R. Cytron, “Doacross: Beyond vectorization for multiprocessors (extended abstract),” in Proc. 1986 Int. Conf. Parallel Processing, pp. 836–844.
    • Proc. 1986 Int. Conf. Parallel Processing , pp. 836-844
    • Cytron, R.1
  • 20
    • 0001047308 scopus 로고
    • Polynomial algorithms for computing the Smith and Hermite normal forms of an integer matrix
    • Nov.
    • R. Kannan and A. Bachem, “Polynomial algorithms for computing the Smith and Hermite normal forms of an integer matrix,” SIAM J. Comput., vol. 8, no. 4, pp. 499–507, Nov. 1979.
    • (1979) SIAM J. Comput. , vol.8 , Issue.4 , pp. 499-507
    • Kannan, R.1    Bachem, A.2
  • 21
    • 0003037829 scopus 로고
    • Algorithms for VLSI array processors
    • Reading, MA: Addison-Wesley sect. 8.3., Mead and L. Conway, Eds.
    • H. T. Kung and C.E. Leiserson, “Algorithms for VLSI array processors,” in Introduction to VLSI Systems, C. Mead and L. Conway, Eds. Reading, MA: Addison-Wesley, 1980, sect. 8.3.
    • (1980) Introduction to VLSI Systems, C
    • Kung, H.T.1    Leiserson, C.E.2
  • 22
    • 0025235634 scopus 로고
    • Mapping nested loop algorithms into multidimensional systolic arrays
    • Jan.
    • P. Lee and Z. M. Kedem, “Mapping nested loop algorithms into multidimensional systolic arrays,” IEEE Trans. Parallel Distributed Syst., vol. 1, pp. 64–76, Jan. 1990.
    • (1990) IEEE Trans. Parallel Distributed Syst. , vol.1 , pp. 64-76
    • Lee, P.1    Kedem, Z.M.2
  • 23
    • 0024143306 scopus 로고
    • Synthesizing linear array algorithms from nested for loop algorithms
    • Dec.
    • —, “Synthesizing linear array algorithms from nested for loop algorithms,” IEEE Trans. Comput., vol. 37, pp. 1578–1598, Dec. 1988.
    • (1988) IEEE Trans. Comput. , vol.37 , pp. 1578-1598
  • 24
    • 0007091743 scopus 로고
    • Multiprocessors: Discussion of theoretical and practical problems
    • Univ. of Illinois at Urbana-Champaign, Rep. UIUCDCS-R-79-990, Nov.
    • D. A. Padua, “Multiprocessors: Discussion of theoretical and practical problems,” Ph. D dissertation, Univ. of Illinois at Urbana-Champaign, Rep. UIUCDCS-R-79-990, Nov. 1979.
    • (1979) Ph. D dissertation
    • Padua, D.A.1
  • 25
    • 0022290106 scopus 로고
    • Optimal systolic implementation of N-dimensional recurrences
    • Y. Wong and J.-M. Delosme, “Optimal systolic implementation of N-dimensional recurrences,” in IEEE Proc. ICCD, 1985, pp. 618–621.
    • (1985) IEEE Proc. ICCD , pp. 618-621
    • Wong, Y.1    Delosme, J.-M.2
  • 26
    • 84942218732 scopus 로고
    • Using RAB to map algorithms into bit-level systolic arrays
    • May
    • V. E. Taylor and J. A. B. Fortes, “Using RAB to map algorithms into bit-level systolic arrays,” in Proc. Int. Conf. Supercomput., May 1987.
    • (1987) Proc. Int. Conf. Supercomput.
    • Taylor, V.E.1    Fortes, J.A.B.2
  • 27
    • 0003914144 scopus 로고    scopus 로고
    • Diophantine Equations
    • New York: Academic
    • L.J. Mordell, Diophantine Equations. New York: Academic, 1969, p. 30.
    • Mordell, L.J.1
  • 28
    • 0024122343 scopus 로고
    • Bit level processor array: Current architectures and a design and a programming tool
    • Helsinki, Finland, June
    • M.T. O’Keefe and J.A.B. Fortes, “Bit level processor array: Current architectures and a design and a programming tool,” in Proc. 1988 Int. Symp. Circuit Syst., Helsinki, Finland, June 1988, pp. 2751–2755.
    • (1988) Proc. 1988 Int. Symp. Circuit Syst. , pp. 2751-2755
    • O’Keefe, M.T.1    Fortes, J.A.B.2
  • 29
    • 0003690189 scopus 로고    scopus 로고
    • Theory of Linear and Integer Programming
    • New York: Wiley
    • A. Schrijver, Theory of Linear and Integer Programming. New York: Wiley, 1986.
    • Schrijver, A.1
  • 30
    • 84942218733 scopus 로고
    • Scheduling, partitioning and mapping of uniform dependence algorithms on processor arrays
    • Purdue Univ, W. Lafayette, IN 47907, May
    • W. Shang, “Scheduling, partitioning and mapping of uniform dependence algorithms on processor arrays,” Ph.D. dissertation, Purdue Univ., W. Lafayette, IN 47907, May 1990.
    • (1990) Ph.D. dissertation
    • Shang, W.1
  • 32
    • 0020589597 scopus 로고
    • On the design of algorithms for VLSI systolic arrays
    • Jan.
    • D. I. Moldovan, “On the design of algorithms for VLSI systolic arrays,” Proc. IEEE, vol. 71, pp. 113–120, Jan. 1983.
    • (1983) Proc. IEEE , vol.71 , pp. 113-120
    • Moldovan, D.I.1
  • 33
    • 0021510147 scopus 로고
    • Systolic array chip matches the pace of high-speed processing
    • Oct., 31
    • R. Davis and D. Thomas, “Systolic array chip matches the pace of high-speed processing,” Electron. Design, Oct. 31, 1984.
    • (1984) Electron. Design
    • Davis, R.1    Thomas, D.2
  • 34
    • 0004039746 scopus 로고    scopus 로고
    • Parallel Computers: Architecture, Programming and Algorithms
    • Bristol, Adam Hilger
    • R.W. Hockney and C. R. Jesshope, Parallel Computers: Architecture, Programming and Algorithms. Bristol, Adam Hilger: 1981, pp. 178–192.
    • Hockney, R.W.1    Jesshope, C.R.2
  • 35
    • 0020126591 scopus 로고    scopus 로고
    • Bit-serial parallel processing systems
    • K. E. Batcher, “Bit-serial parallel processing systems,” IEEE Trans. Comput., vol. C-31, no. 5, pp. 377–384.
    • IEEE Trans. Comput. , vol.C-31 , Issue.5 , pp. 377-384
    • Batcher, K.E.1
  • 36
    • 84936895788 scopus 로고
    • Systolic array—From concept to implementation
    • July
    • J. A. B. Fortes and B. W. Wah, “Systolic array—From concept to implementation,” IEEE Comput. Mag., pp. 12–17, July 1987.
    • (1987) IEEE Comput. Mag. , pp. 12-17
    • Fortes, J.A.B.1    Wah, B.W.2
  • 37
    • 0026986334 scopus 로고
    • One-to-one time mappings of nested algorithms into lower dimensional processor arrays
    • Mar., Beverly Hills, CA
    • Z. Yang, W. Shang, and J. A. B. Fortes, “One-to-one time mappings of nested algorithms into lower dimensional processor arrays,” in Proc. Sixth IEEE Int. Parallel Processing Symp., Mar. 1992, Beverly Hills, CA, pp. 156–164.
    • (1992) Proc. Sixth IEEE Int. Parallel Processing Symp. , pp. 156-164
    • Yang, Z.1    Shang, W.2    Fortes, J.A.B.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.