Effective built-in self-test for booth multipliers

IEEE Design and Test of Computers

Volumn 15, Issue 3, 1998, Pages 105-111

  Gizopoulos, Dimitris ^a,c,d,e,f   Paschalis, Antonis ^a,d,f,g,h   Zorian, Yervant ^b,d,i,j,k  

^a INSTITUTE OF NANOSCIENCE AND NANOTECHNOLOGY   (Greece)

^b LogicVision ^*  (United States)

^c INSTITUTE OF INFORMATICS AND TELECOMMUNICATIONS   (Greece)

^d IEEE

^e UNIVERSITY OF PATRAS   (Greece)

^f UNIVERSITY OF ATHENS   (Greece)

^g Digital Design and Testing Group   (Netherlands)

^h Europ Test Technol Tech Comm S

ⁱ LogicVision Inc   (United States)

^j UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

^k MCGILL UNIVERSITY   (Canada)

more..

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; MULTIPLYING CIRCUITS; SHIFT REGISTERS; TIMING CIRCUITS;

BOOTH MULTIPLIERS; BUILT IN SELF TEST (BIST) SCHEMES;

INTEGRATED CIRCUIT TESTING;

EID: 0032120999     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/54.706041     Document Type: Article

References (10)

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5. V.D. Agrawal et al., "Built-In Self-Test for Digital Integrated Circuits," AT&T Technical J., Mar./Apr. 1994, pp. 30-39.
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