A time-delay digital tanlock loop

ISSPA 1999 - Proceedings of the 5th International Symposium on Signal Processing and Its Applications

Volumn 1, Issue , 1999, Pages 391-394

  Hussain, Zuhir M ^a   Boashash, Boualem ^a   Al Araji, Saleh R ^a  

^a QUEENSLAND UNIVERSITY OF TECHNOLOGY   (Australia)

Author keywords

[No Author keywords available]

Indexed keywords

TIME DELAY;

CIRCUIT PARAMETER; DIGITAL TANLOCK LOOP; FIRST-ORDER; IMPORTANT FEATURES; PRACTICAL PROBLEMS; TIME-DELAY DIGITAL TANLOCK LOOPS;

DELAY CIRCUITS;

EID: 0000828822     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSPA.1999.818194     Document Type: Conference Paper

References (8)

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5. R. Hati et al, "On the performance of a modified first-order tanlock digital phase-locked loop(DPLL)," Journal of Electrical and Electronics Engineering-Australia, June 1998.
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8. H. C. Osborne, "Stability analysis of an N-th power digital phase-locked loop-Part U: Second-and third-order DPLL's," IEEE Trans. Com., COM-28, Aug. 1980.