Design of a Temporal Learning Chip for Signal Generation and Classification

Analog Integrated Circuits and Signal Processing

Volumn 18, Issue 2-3, 1999, Pages 229-242

  Salam, Fathi M ^a   Oh, Hwa Joon ^b,c,d  

^a Michigan State University   (United States)

^b Hyundai Electronics America   (United States)

^c Yonsei University   (South Korea)

^d MICHIGAN STATE UNIVERSITY   (United States)

Author keywords

2 D arrays; Analog VLSI; Recurrent neural networks; Signal classification; Temporal learning chip

Indexed keywords

ALGORITHMS; LEARNING SYSTEMS; VLSI CIRCUITS;

TEMPORAL LEARNING CHIPS;

NEURAL NETWORKS;

EID: 0000555782     PISSN: 09251030     EISSN: None     Source Type: Journal    
DOI: 10.1023/a:1008315507084     Document Type: Article

References (10)

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4. Hwa-Joon Oh and Fathi M. Salam, "Design of a Temporal Learning Chip for Signal Generation and Classification." Proc. of The 1997 IEEE International Symposium on Circuit and Systems Hong Kong, pp. 689-692, 1997.
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10. Fathi M. Salam, "A Neuro-Chip with Temporal Learning:Test Results for Signal/Shape Generation." Proc. of The 31-st Asilomar Conference on Signals, Systems, and Computers Asilomar, CA, 1997.