Design of a temporal learning chip for signal generation and classification

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 1, Issue , 1997, Pages 689-692

  Oh, Hwa Joon ^a   Salam, Fathi M ^a  

^a Hyundai Electronics America   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; ARRAYS; BACKPROPAGATION; CMOS INTEGRATED CIRCUITS; COMPUTER HARDWARE; COMPUTER SIMULATION; INTEGRATED CIRCUIT LAYOUT; LEARNING SYSTEMS; MICROPROCESSOR CHIPS; TECHNOLOGY; VLSI CIRCUITS;

LEARNING CHIP; LEARNING RULE; SIGNAL CLASSIFICATION; SIGNAL GENERATION; SOFTWARE PACKAGE PSPICE;

NEURAL NETWORKS;

EID: 0030652873     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)