Identification Of Perimeter Depletion And Emitter Plug Effects In Deep-Submicrometer, Shallow-Junction Polysilicon Emitter Bipolar Transistors

IEEE Transactions on Electron Devices

Volumn 39, Issue 6, 1992, Pages 1477-1489

  Burghartz, Joachim N ^a   Sun, Jack Yuan Chen ^a   Stanis, Carol L ^a   Mader, Siegfried R ^a   Warnock, James D ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 0000211812     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.137329     Document Type: Article

References (46)

1. M. Takagi, K. Nakayama, Ch. Nevada, and H. Kamioko, “Improvement of shallow base transistor technology by using a doped polysil icon diffusion source,” J. Japan. Soc. Appl. Phys. (Suppl.), vol. 42, pp. 101–109, 1972.
2. H. Murrmann and A. Glasl, “Der Polysil-Emitter— Eine neue Technologic fur verbesserte Transistoreigenschaften,” presented at the 6th Int. Congr. Microelectr., Muenchen, Germany, 1974.
3. J. Graul, A. Glasl, and H. Murrmann, “High-performance transistors with arsenic-implanted Polysil emitters,” IEEE J. Solid-State Circuits, vol. SC-11, pp. 491–495, 1976.
4. H. C. De Graaff and J. G. De Groot, “The SIS tunnel emitter: A theory for emitters with thin interface layers,” IEEE Trans. Electron Devices, vol. ED-26, pp. 1771–1776, 1979.
5. J. G. Fossum and M. A. Shibib, “A minority-carrier transport model for polysilicon contacts to silicon bipolar devices, including solar cells,” in IEDM Tech. Dig., 1980, pp. 280–283.
6. H. Ryssel, H. Iberl, M. Bleier, G. Prinke, K. Haberger, and H. Kranz, “Arsenic-implanted polysilicon layers,” Appl. Phys., vol. 24, pp. 197–200, 1981.
7. A. Neugroschel, M. Arienzo. Y. Komem, and R. D. Issac, “Experimental study of the minority-carrier transport at the polysilicon-monosilicon interface,” IEEE Trans. Electron Devices, vol. ED-32, no. 4, pp. 807–816, 1985.
8. E. Crabbé, S. Swirhun, J. del Alamo, R. F. W. Pease, and R. M. Swanson, “Majority and minority carrier transport in polysilicon emitter contacts,” in IEDM Tech. Dig., 1986, pp. 28–31.
9. T. H. Ning and R. D. Issac, “Effects of emitter contact on current gain of silicon bipolar transistors,” IEEE Trans. Electron Devices, vol. ED-27, no. 11, pp. 2051–2055, 1980.
10. E. F. Chor, P. Ashbum, and A. Brunnschweiler, “Emitter resistance of arsenic- and phosphorus-doped polysilicon emitter transistors,” IEEE Electron Devices Lett., vol. EDL-6, no. 10, pp. 516–518, 1985.
11. G. Patton, J. C. Bravman, and J. D. Plummer, “Physics, technology and modeling of polysilicon emitter contacts for VLSI bipolar transistors,” IEEE Trans. Electron Devices, vol. ED-33, no. 11, pp. 1754–1768, 1986.
12. B. Y. Tsaur and L. S. Hung, “Epitaxial alignment of polycrystalline Si films on (100) Si,” Appl. Phys. Lett., vol. 37. no. 7, pp. 648–651, 1980.
13. H. B. Harrison, S. T. Johnson, C. Wong, Y. Komem, and S. Cohen, “Using rapid thermal processing to induce epitaxial alignment of polycrystalline silicon films on (100) silicon,” Mater. Res. Soc. Symp. Proc., vol. 71, pp. 455–458, 1986.
14. J. L. Hoyt, E. F. Crabbé, R. F. W. Pease, and J. F. Gibbons, “Lateral uniformity of n +/p junctions formed by arensic diffusion from epitaxially aligned polycrystalline silicon on silicon,” J. Electrochem. Soc., vol. 135, no. 7, pp. 1773–1779, 1988.
15. C. T. Chuang, G. P. Li, and T. H. Ning, “Effects of off-axis implant on the characteristics of advanced self-aligned bipolar transistors,” IEEE Electron Device Lett., vol. EDL-8, no. 7, pp. 321–323, 1987.
16. Th. I. Kamins, “Effect of polysilicon-emitter shape on dopant diffusion in polysilicon-emitter transistors,” IEEE Electron Device Lett., vol. 10, no. 9, pp. 401–404, 1989.
17. J. N. Burghartz, J. Y.-C. Sun, S. R. Mader, C. L. Stanis, and B. J. Ginsberg, “Perimeter and plug effects in deep submicron polysilicon emitter bipolar transistor,” in Tech. Dig. 1990 Symp. on VLSI Technology (Honolulu, HI), pp. 55–56.
18. A. Gover and A. Gaash, “Experimental model aid for planar design of transistor characteristics in integrated circuits,” Solid-State Electron., vol. 19, pp. 125–127, 1976.
19. H. M. Rein, “A simple method for separation of the internal and external (peripheral) currents of bipolar transistors,” Solid-State Electron., vol. 27, no. 7, 625–631, 1984.
20. E. H. Stevens, “Saturation currents in smaller-geometry bipolar transistors,” IEEE Trans. Electron Devices, vol. ED-31, no. 1, pp. 80–82, 1984.
21. M. Miura-Mattausch, J. Rüstig, and R. Kircher, “Dependence of current gain β on spacer geometry and emitter size in polysilicon self-aligned bipolar transistors,” Solid-State Electron., vol. 33, no. 3, pp. 325–331, 1990.
22. G. P. Li, C. T. Chuang, T. C. Chen, and T. H. Ning, “On the narrow-emitter effect of advanced shallow-profile bipolar transistors,” IEEE Trans. Electron Devices, vol. 35, no. 11, pp. 1942–1950, 1988.
23. C. T. Chuang, “Performance degradation due to extrinsic base encroachment in advanced narrow-emitter bipolar circuits—Part I: Basic inverter and Part II: Non-threshold logic circuits,” IEEE Trans. Electron Devices, vol. 36, no. 9, pp. 1751–1763, 1989.
24. J. N. Burghartz, B. J. Ginsberg, and S. R. Mader, “New technology for bipolar emitters in the deep submicron range,” in Tech. Dig. 1989 Symp. on VLSI Technology (Kyoto, Japan, 1989), pp. 57–58.
25. B. S. Meyerson, “Low-temperature silicon epitaxy for ultrahigh vacuum/chemical vapor deposition,” Appl. Phys. Lett., vol. 48, pp. 797–799, 1986.
26. J. N. Burghartz, S. R. Mader, B. S. Meyerson, B. J. Ginsberg, J. M. C. Stork, C. L. Stanis, and J. Y.-C. Sun, “Self-aligned bipolar NPN transistor with 60 nm epitaxial base,” in IEDM Tech. Dig. (Washington, DC, 1989), pp. 229–232.
27. J. N. Burghartz, S. R. Mader, B. J. Ginsberg, B. S. Meyerson, J. M. C. Stork, C. L. Stanis, J. Y. -C. Sun, and M. R. Polcari, “Self-aligned bipolar epitaxial base NPN transistors by selective epitaxy emitter window (SEEW) technology,” IEEE Trans. Electron Devices, vol. 38, no. 2, pp. 378–385, 1991.
28. R. Angelucci, C. Y. Wong, J. Y. -C. Sun, G. Scilla, P. A. Mc-Farland, and A. C. Megdanis, “Characteristics of arsenic doped polycrystalline silicon-gate capacitors after rapid thermal processing,” in 1988 Mat. Res. Soc. Symp. Proc., vol. 106, pp. 285–290.
29. M. Arienzo, Y. Komem, and A. E. Michel, “Diffusion of arsenic in bilayer polycrystalline silicon films,” J. Appl. Phys., vol. 55, no. 2, pp. 365–369, 1984.
30. T. H. Ning, R. D. Isaac, P. M. Solomon, D. D. Tang, H.-N. Yu, G. C. Feth, and S. K. Wiedmann, “Self-aligned bipolar transistors for high-performance and low-power-delay VLSI,” IEEE Trans. Electron. Devices, vol. ED-28, no. 9, pp. 1010–1013, 1981.
31. S. M. Hu and S. Schmidt, “Interactions in sequential diffusion processes in semiconductors,” J. Appl. Phys., vol. 39, no. 9, pp. 4272–4283, 1968.
32. J. M. C. Stork, M. Arienzo, and C. Y. Wong, “Correlation between the diffusive and electrical barrier properties of the interface in polysilicon contacted n + -p junctions,” IEEE Trans. Electron Devices, vol. ED-32, no. 9, pp. 1766–1770, 1985.
33. Y. H. Kwark, “SIPOS heterojunction contacts to silicon,” Ph.D. dissertation, Stanford Electron. Labs., Stanford, CA. May 1985.
34. A. Cuthbertson and P. Ashburn, “An investigation of the tradeoff between enhanced gain and base doping in polysilicon emitter bipolar transistors,” IEEE Trans. Electron Devices, vol. ED-32, no. 11, pp. 2399–2407, 1985.
35. G. P. Li, E. Hackbarth, and T.-C. Chen, “Identification and implication of a perimeter tunneling current component in advanced self-aligned bipolar transistors,” IEEE Trans. Electron Devices, vol. 35, no. 1, pp. 89–95, 1988.
36. J. C. S. Woo, J. D. Plummer, and J. M. C. Stork, “Non-ideal base current in bipolar transistors at low temperatures,” IEEE Trans. Electron Devices, vol. ED-34, no. 1, pp. 130–138, 1987.
37. S. G. Chamberlain and D. J. Roulston, “Modeling of emitter-bulk and peripheral space-charge-layer recombination currents in bipolar transistors,” IEEE Trans. Electron. Devices, vol. ED-23, pp. 1345–1346. 1976.
38. A. Neugroschel and J. A. Mazer, “Effects of grain boundaries on the currentvoltage characteristics of polycrystalline silicon solar cells,” IEEE Trans. Electron Devices, vol. ED-29, no. 2, pp. 225–236, 1982
39. G. R. Wolstenholme, D. C. Browne, P. Ashbum, and P. T. Lands-berg, “An investigation of the transition from polysilicon emitter to SIS emitter behavior,” IEEE Trans. Electron Devices, vol. 35, no. 11, pp. 1915–1923, 1988.
40. B. Faughnan and A. C. Ipri, “A study of hydrogen passivation of grain boundaries in polysilicon thin-film transistors,” IEEE Trans. Electron. Devices, vol. 36, no. 1, pp. 101–107, 1989.
41. B. Yun, B. Cunningham, J. Snare, K. Bames, and R. C. Lange, in Tech. Dig. J99J BCTM, pp. 267–270.
42. M. C. Wilson, D. Gold, P. C. Hunt, and G. R. Booker, “The effect of emitter sidewall isolation on the emitter junction in a double layer polysilicon bipolar process,” in Tech. Dig. 1988 BCTM, pp. 128–131.
43. J. M. C. Stork, D. L. Harame, B. S. Meyerson, and T. N. Nguyen, “High performance operation of silicon bipolar transistors at liquid nitrogen temperature,” in IEDM Tech. Dig., 1987, pp. 405–408.
44. T. Aoyama, C. Ogawa, M. Sugiyama, H. Takemura, F. Toyokawa, M. Sakamoto, and T. Tshiro, “Selective polysilicon deposition (SPD) by hot-wall LPCVD and its application to high speed bipolar devices,” in Extended Abstr. 22nd Conf on Solid State Devices and Materials (Sendai, Japan), 1990, pp. 665–668.
45. J. N. Burghartz et al., “Novel in situ doped polysilicon emitter process with buried diffusion source (BDS),” IEEE Electron Device Lett., vol. 12, no. 12, pp. 679–681, 1991.
46. J. D. Cressler, D. D. Tang, and E. S. Yang, “Injection induced bandgap narrowing and its effects on the low temperature operation of silicon bipolar transistors,” IEEE Trans. Electron Devices, vol. 36, no. 11, pp. 2576–2586, 1989.