Temperature scaling for 35 nm gate length high-performance CMOS

Materials Science in Semiconductor Processing

Volumn 7, Issue 4-6 SPEC. ISS., 2004, Pages 369-374

  Feudel, Th ^a   Horstmann, M ^a   Gerhardt, M ^a   Herden, M ^a   Herrmann, L ^a   Gehre, D ^a   Krueger, Ch ^a   Greenlaw, D ^a   Raab, M ^a  

^a IBM MICROELECTRONICS   (United States)

Author keywords

CMOS; Implantation; Nanotechnology

Indexed keywords

ANNEALING; CAPACITANCE; CMOS INTEGRATED CIRCUITS; ELECTRIC CURRENTS; ELECTRIC POTENTIAL; NANOTECHNOLOGY; PARAMETER ESTIMATION; PROBLEM SOLVING; TRANSISTORS;

GATE LENGTH; IMPLANTATION; SOURCE-DRAIN-EXTENSION (SDE) JUNCTION DEPTH; TEMPERATURE SCALING;

HIGH TEMPERATURE EFFECTS;

EID: 9544252206     PISSN: 13698001     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mssp.2004.09.063     Document Type: Conference Paper

References (5)

1. Fukutome H, et al. Proceedings of the IEDM 2003. p. 485.
2. Greenlaw D, et al. Proceedings of the IEDM 2003. p. 277.
3. Lindsay R, et al. Proceedings of the MRS 2002. vol. 717, p. 65.
4. Shima A, et al. Proceedings of the IEDM 2003. p. 493.
5. Horstmann M, et al. E-MRS spring meeting 2004, Symposium B, Strasbourg, accepted for publication.