Statistical signal integrity analysis and diagnosis methodology for high-speed systems

IEEE Transactions on Advanced Packaging

Volumn 27, Issue 4, 2004, Pages 611-629

  Matoglu, Erdem ^a   Pham, Nam ^a   de Araujo, Daniel N ^a   Cases, Moises ^a   Swaminathan, Madhavan ^b  

^a IBM   (United States)

^b TSRB   (United States)

Author keywords

Design of experiments; Design space exploration; Parametric yield; Source synchronous systems; Statistical diagnosis; Statistical signal integrity analysis

Indexed keywords

COMPUTER AIDED ANALYSIS; COMPUTER SIMULATION; DATA COMMUNICATION SYSTEMS; DESIGN FOR TESTABILITY; MULTIPROCESSING SYSTEMS; PROBABILITY DISTRIBUTIONS; STATISTICAL METHODS; VISUALIZATION;

DESIGN OF EXPERIMENTS; DESIGN SPACE EXPLORATION; HIGH SPEED SYSTEMS; SOURCE SYNCHRONOUS SYTEMS; STATISTICAL SIGNAL INTEGRITY ANALYSIS; STATISTICAL SIGNAL INTEGRITY DIAGNOSIS;

INTEGRATED CIRCUIT LAYOUT;

EID: 9244231804     PISSN: 15213323     EISSN: None     Source Type: Journal    
DOI: 10.1109/TADVP.2004.831856     Document Type: Article

References (29)

1. S. G. Duvall, "Statistical circuit modeling and optimization," in Proc. Int. Statistical Metrology Workshop 2000, June 2000, pp. 56-63.
2. E. Laermans, F. Olyslager, and D. D. Zutter, "Sensitivity based statistical analysis of multiconductor transmission lines in multilayered media," in Proc. Int. Symp. of Antennas Propagation Society, July 1996, pp. 288-291.
3. T. Mikazuki and N. Matsui, "Statistical design techniques for high-speed circuit boards with correlated structure distributions," IEEE Trans. Comp. Packag. Manufact. Technol., vol. 17, pp. 159-165, Mar. 1994.
4. Q. J. Zhang and M. Nakhla, "Yield analysis and optimization of VLSI interconnects in multichip modules," in Proc. IEEE Multi-Chip Module Conf., Mar. 1993, pp. 160-163.
5. L. L. Li, Q. J. Zhang, and M. Nakhla, "A moment method for statistical analysis of high speed VLSI interconnects," in Proc. IEEE Custom Integrated Circuit Conf., May 1994, pp. 305-308.
6. B. Young, Digital Signal Integrity. Englewood Cliffs, NJ: Prentice-Hall, 2001.
7. J. M. Hammersley and D. C. Handscomb, Monte Carlo Methods. New York: Chapman & Hall, 1964. reprinted, 1983.
8. T. B. Barker, Quality by Experimental Design. New York: Marcel Dekker, 1994.
9. J. Chen and M. A. Styblinski, "A systematic approach of statistical modeling and its application to CMOS circuits," in Proc. IEEE Int. Symp. Circuits Systems, May 1993, pp. 1805-1808.
10. G. Taguchi, Introduction to Quality Engineering. Dearborn, MI: Amer. Supplier Ins., Inc., 1986.
11. P. J. Ross, Taguchi Techniques for Quality Engineering. New York: McGraw-Hill, 1995.
12. M. S. Phadke, Quality Engineering Using Robust Design. Englewood Cliffs, NJ: Prentice-Hall, 1989.
13. R. L. Mason, R. F. Gunst, and J. L. Hess, Statistical Design and Analysis of Experiments: With Applications to Engineering and Science. New York: Wiley, 1989.
14. N. Pham, M. Cases, and J. Bandyopadhyay, "Design, modeling, and simulation methodology for source synchronous DDR memory subsystems," in Proc. IEEE Electronic Components Technology Conf., May 2000, pp. 21-24.
15. N. Pham, M. Cases, and D. Guertin, "Design and packaging challenges for on-board cache subsystems using source synchronous 400 Mb/s interfaces," in Proc. IEEE Electronic Components Technology Conference, May 2001, pp. 123-127.
16. T. Arabi, J. Jones, G. Taylor, and D. Riendeau, "Modeling, simulation, and design methodology of the interconnect and packaging of an ultra-high speed source synchronous bus," in Proc. IEEE Electrical Performance Electronic Packaging, Oct. 1998, pp. 26-28.
17. Hspice 2001.2, Avanti Corp., Fremont, CA, 2001.
18. M. H. Kutner, C. J. Nachtschiem, W. Wasserman, and J. Neter, Applied Linear Statistical Models. New York: McGraw-Hill, 1996.
19. A. Leon-Garcia, Probability and Random Processes for Electrical Engineering. Toronto, ON, Canada: Addison-Wesley, 1989.
20. A. Papoulis, Probability, Random Variables, and Stochastic Processes New York: McGraw-Hill, 1984.
21. R. Spence and R. R. Soin; Tolerance Design of Electronic Circuits London, UK: Imperial College Press, 1997.
22. S. M. Ross, Introduction to Probability Models. San Diego, CA: Harcourt, 2000.
23. H. Yoon, P. Variyam, A. Chatterjee, and N. Nagi, "Hierarchical statistical inference model for specification based testing of analog circuits," in Proc. IEEE VLSI Test Symp., Apr. 1998, pp. 145-150.
24. T. K. Moon and W. C. Stirling, Mathematical Methods and Algorithms for Signal Processing. Englewood Cliffs: Prentice-Hall; 2000.
25. PCI-SIG (2003). [Online]. Available: http://www.pcisig.com/specifications
26. L. D. Paulson, "The ins and outs of new local I/O trends," IEEE Computer, vol. 36, pp. 13-16, July 2003.
27. M. Cases and N. Pham, "Design, modeling, and simulation methodology for PCI-X subsystems," in Proc. IEEE Electrical Performance Electronic Packaging Conf., Oct. 2000, pp. 33-36.
28. M. G. Scottis, M. Krunz, and M. M. K. Liu, "Enhancing the PCI bus to support real-time streams," in Proc. IEEE Performance, Computing, Communications Conf., Feb. 1999, pp. 303-309.
29. P. J. Bickel and K. A. Doksum, Mathematical Statistics. San Fransisco, CA: Holden-Day, 1977.