-
1
-
-
0016961262
-
On-chip high-voltage generation in MNOS integrated circuits using an improved voltage multiplier technique
-
J. F. Dickson, "On-chip high-voltage generation in MNOS integrated circuits using an improved voltage multiplier technique," IEEE J. Solid-State Circuits, vol. 11, pp. 374-378, 1976.
-
(1976)
IEEE J. Solid-state Circuits
, vol.11
, pp. 374-378
-
-
Dickson, J.F.1
-
2
-
-
0031210141
-
A dynamic analysis of the Dickson charge pump circuit
-
Aug.
-
T. Tanzawa and T. Tanaka, "A dynamic analysis of the Dickson charge pump circuit," IEEE J. Solid-State Circuits, vol. 32, pp. 1231-1240, Aug. 1997.
-
(1997)
IEEE J. Solid-state Circuits
, vol.32
, pp. 1231-1240
-
-
Tanzawa, T.1
Tanaka, T.2
-
3
-
-
0031340143
-
Floating-well charge pump circuits for sub-2.0V single power supply flash memories
-
Jun.
-
K. H. Choi, J. M. Park, J. K. Kim, T. S. Jung, and K. D. Suh, "Floating-well charge pump circuits for sub-2.0V single power supply Flash memories," Symp. VLSI Circuits Dig. Tech. Papers, pp. 61-62, Jun. 1997.
-
(1997)
Symp. VLSI Circuits Dig. Tech. Papers
, pp. 61-62
-
-
Choi, K.H.1
Park, J.M.2
Kim, J.K.3
Jung, T.S.4
Suh, K.D.5
-
4
-
-
0034247158
-
A new charge pump without degradation in threshold voltage due to body effect
-
Aug.
-
J. S. Shin, I. Y. Chung, Y. J. Park, and H. S. Min, "A new charge pump without degradation in threshold voltage due to body effect," IEEE J. Solid-State Circuits, vol. 35, pp. 1227-1230, Aug. 2000.
-
(2000)
IEEE J. Solid-state Circuits
, vol.35
, pp. 1227-1230
-
-
Shin, J.S.1
Chung, I.Y.2
Park, Y.J.3
Min, H.S.4
-
5
-
-
0001050518
-
MOS charge pumps for low-voltage operation
-
Apr.
-
J. T. Wu and K. L. Chang, "MOS charge pumps for low-voltage operation," IEEE J. Solid-State Circuits, vol. 33, pp. 592-597, Apr. 1998.
-
(1998)
IEEE J. Solid-state Circuits
, vol.33
, pp. 592-597
-
-
Wu, J.T.1
Chang, K.L.2
-
6
-
-
0026953337
-
A 5-v-only operation 0.6um flash EEPROM with row decoder scheme in triple-well structure
-
Nov.
-
A. Umezawa, S. Atsumi, M. Kuriyama, H. Banba, K. ichi Imamiya, K. Naruke, S. Tamada, E. Obi, M. Oshikiri, T. Suzuki, and S. Tanaka, "A 5-v-only operation 0.6um flash EEPROM with row decoder scheme in triple-well structure," IEEE J. of Solid-State Circuits, vol. 27, pp. 1540-1545, Nov. 1992.
-
(1992)
IEEE J. of Solid-state Circuits
, vol.27
, pp. 1540-1545
-
-
Umezawa, A.1
Atsumi, S.2
Kuriyama, M.3
Banba, H.4
Ichi Imamiya, K.5
Naruke, K.6
Tamada, S.7
Obi, E.8
Oshikiri, M.9
Suzuki, T.10
Tanaka, S.11
-
7
-
-
0003774931
-
Novel high positive and negative pumping circuits for low supply voltage
-
H. C. Lin, K. H. Chang, and S. C. Wong, "Novel high positive and negative pumping circuits for low supply voltage," Proc. IEEE ISCAS'99, vol. I, pp. 238-241.
-
Proc. IEEE ISCAS'99
, vol.1
, pp. 238-241
-
-
Lin, H.C.1
Chang, K.H.2
Wong, S.C.3
-
8
-
-
84881096485
-
A high-efficiency CMOS charge pump circuit
-
May
-
S. Y. Lai and J. S. Wang, "A high-efficiency CMOS charge pump circuit," Symp. IEEE ISCAS'01, vol. 4, pp. 406-409, May 2001.
-
(2001)
Symp. IEEE ISCAS'01
, vol.4
, pp. 406-409
-
-
Lai, S.Y.1
Wang, J.S.2
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