A 90nm high volume manufacturing logic technology featuring Cu metallization and CDO low κ ILD interconnects on 300 mm wafers

Proceedings of the IEEE 2004 International Interconnect Technology Conference

Volumn , Issue , 2004, Pages 205-207

  Jan, C H ^a   Anand, N ^a   Allen, C ^a   Bielefeld, J ^a   Buehler, M ^a   Chikamane, V ^a   Fischer, K ^a   Jain, A ^a   Jeong, J ^a   Kliopcic, S ^a   Marieb, T ^a   Miner, B ^a   Nguyen, P ^a   Schmitz, A ^a   Nashner, M ^a   Scherban, T ^a   Schroeder, B ^a   Ward, C ^a   Wu, R ^a   Zawadzki, K ^a   Thompson, S ^a   Bohr, M ^a   more..

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHEMICAL BONDS; CHEMICAL VAPOR DEPOSITION; COPPER; DOPING (ADDITIVES); ELECTROMIGRATION; FOURIER TRANSFORM INFRARED SPECTROSCOPY; METALLIZING; MICROPROCESSOR CHIPS; PERMITTIVITY; THERMAL EXPANSION; TRANSMISSION ELECTRON MICROSCOPY;

COEFFICIENT OF THERMAL EXPANSION (CTE); COPPER DOPING OXIDE (CDO); CRITICAL DIMENSIONS (CD); INTERCONNECT TECHNOLOGY;

INTERCONNECTION NETWORKS;

EID: 8644249836     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)

1. S. Thompson et al., IEDM Tech Dig., 2002, pp 61-64
2. C.-H. Jan et al., IITC Tech Dig, 2003, pp 15-17