Process optimisation and dual damascene integration of porous CVD SiOC dielectric at 2.4 and 2.2 k-values for 45 nm CMOS technology

Proceedings of the IEEE 2004 International Interconnect Technology Conference

Volumn , Issue , 2004, Pages 202-204

  Arnal, V ^a   Hoofman, R J O M ^b   Assous, M ^c   Bancken, P H L ^b   Broekaart, M ^d   Brun, P ^c   Casanova, N ^a   Chapelon, Ll ^a   Chevolleau, T ^f   Cowache, C ^a   Daamen, R ^b   Farcy, A ^a   Fayolle, M ^c   Feldis, H ^a   Furukawa, Y ^b   Goldberg, C ^e   Gosset, L G ^d   Guedj, C ^c   Haxaire, K ^a   Hinsinger, O ^a   Josse, E ^a   Jullian, S ^d   Louveau, O ^a   Michelon, J ^b   Posseme, N ^a   Rivoire, M ^a   Roman, A ^a   Vandeweyer, T ^b   Verheijden, G J A M ^b   Torres, J ^a   more..

^a STMICROELECTRONICS   (France)

^b PHILIPS RESEARCH LABORATORIES   (Netherlands)

^c CEA GRENOBLE   (France)

^d NXP SEMICONDUCTORS   (Netherlands)

^e MOTOROLA INC   (United States)

^f Laboratoire Interdisciplinaire de Physique   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CHEMICAL MECHANICAL POLISHING; CHEMICAL VAPOR DEPOSITION; CMOS INTEGRATED CIRCUITS; CROSSTALK; ETCHING; LEAKAGE CURRENTS; LSI CIRCUITS; POROUS MATERIALS; SILICON COMPOUNDS;

DUAL DAMASCENE (DD); ETCH STOP LAYERS (ESL); SIGNAL PROPAGATION; ULTRA LOW-K DIELECTRICS;

DIELECTRIC MATERIALS;

EID: 8644248353     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. L.P. Li et Al. VLSI 2003.
2. H. Ohtake et Al. IEDM 2003.
3. N. Posseme et Al. ECS 2003.
4. Y. L. Yang et Al. IITC 2003.