Multi-core Devices for Safety-critical Systems: A Survey

ACM Computing Surveys

Volumn 53, Issue 4, 2020, Pages

  Cerrolaza, Jon Perez ^a   Obermaisser, Roman ^b   Abella, Jaume ^c   Cazorla, Francisco J ^c   Grüttner, Kim ^d   Agirre, Irune ^a   Ahmadian, Hamidreza ^b   Allende, Imanol ^a  

^a IK4 IKERLAN   (Spain)

^b UNIVERSITY OF SIEGEN   (Germany)

^c BARCELONA SUPERCOMPUTING CENTER   (Spain)

^d OFFIS INSTITUTE FOR INFORMATION TECHNOLOGY   (Germany)

Author keywords

diagnostic coverage; Fault tolerance; spatial independence; time independence

Indexed keywords

SECURITY SYSTEMS; SURVEYS;

DEVICE ABSTRACTIONS; DIAGNOSTIC COVERAGE; ON-CHIP INTEGRATION; SAFETY CERTIFICATION; SAFETY CRITICAL SYSTEMS; SAFETY REQUIREMENTS; TECHNICAL REQUIREMENT; TEMPORAL AND SPATIAL;

SAFETY ENGINEERING;

EID: 85092166002     PISSN: 03600300     EISSN: 15577341     Source Type: Journal    
DOI: 10.1145/3398665     Document Type: Review

References (205)

1. Xavier Jean, Marc Gatti, Guy Berthon, and Marc Fumey. 2012. MULCORS-Use of Multicore Processors in Airborne Systems (EASA Project. 2011/6). Technical Report. EASA. Retrieved from https://www.easa.europa.eu/sites/default/files/dfu/CCC-12-006898REV07%20-%20MULCORS%20Final%20Report.pdf.
2. WSTS. 2018. World semiconductor trade statistics (WSTS). Retrieved from https://www.wsts.org/.
3. Intel. 2020. Case Study, Intel Core 2 Duo Processor on KUKA Robot Controller. Retrieved from https://www.intel.com/content/dam/doc/case-study/industrialCore-kuka-study.pdf .
4. J. Abella and F. J. Cazorla. 2017. Chapter 9Harsh computing in the space domain. In Rugged Embedded Syst., Augusto Vega, Pradip Bose, and Alper Buyuktosunoglu (Eds.). Morgan Kaufmann, Boston, 267-293. DOI:https://doi.org/10.1016/B978-0-12-802459-1.00009-9
5. J. Abella, F. J. Cazorla, E. Quinones, A. Grasset, S. Yehia, P. Bonnot, D. Gizopoulos, R. Mariani, and G. Bernat. 2011. Towards improved survivability in safetyCritical systems. In Proceedings of the IEEE 17th International On-Line Testing Symposium (IOLTS'11). 240-245.
6. J. Abella, C. Hernandez, E. Quinones, F. J. Cazorla, P. R.commy, M. Azkarate-Askasua, J. Perez, E. Mezzetti, and T. Vardanega. 2015. WCET analysis methods: Pitfalls and challenges on their trustworthiness. In Proceedings of the 10th IEEE International Symposium on Industrial Embedded Systems (SIES'15). DOI:https://doi.org/10.1109/SIES.2015. 7185039
7. A. Agarwal, L. Bao, J. Brownet al. 2007. The tile processor (TM) architecture: Embedded multicore for networking and digital multimedia. In Proceedings of the 19th IEEE Hot Chips Symposium (HCS'07). 1-12. DOI:https://doi.org/10.1109/HOTCHIPS.2007.7482495
8. I. Agirre, J. Abella, M. Azkarate-Askasua, and F. J. Cazorla. 2017. On the tailoring of CAST-32A certification guidance to real COTS multicore architectures. In Proceedings of the 12th IEEE International Symposium on Industrial Embedded Systems (SIES'17). 1-8.
9. I. Agirre, M. Azkarate-Askasua, A. Larrucea, J. Perez, T. Vardanega, and F. J. Cazorla. 2015. A safety concept for a railway mixedCriticality embedded system based on multicore partitioning. In Proceedings of the IEEE International Conference on Computers and Information Technology; Ubiquitous Computer and Communication; Dependable, Autonomic and Secure Computing; Pervasive Intelligence and Computing (CIT/IUCC/DASC/PICom'15). 1780-1787. DOI:https://doi.org/10.1109/CIT/IUCC/DASC/PICOM.2015.268
10. I. Agirre, M. Azkarate-askasua, A. Larrucea, J. Perez, T. Vardanega, and F. J. Cazorla. 2016. Automotive safety concept definition for mixedCriticality integration on a COTS multicore. In Computer Safety, Reliability, and Security, A. Skavhaug, J. Guiochet, E. Schoitsch, and F. Bitsch (Eds.). Springer, 273-285.
11. A. Agrawal, G. Fohler, J. Freitag, J. Nowotsch, S. Uhrig, and M. Paulitsch. 2017. Contention-aware dynamic memory bandwidth isolation with predictability in COTS multicores: An avionics case study. In Proceedings of the 29th Euromicro Conference on Real-Time Systems (ECRTS'17).
12. H. Ahmadian, R. Obermaisser, and J. Perez. 2018. Distributed Real-Time Architecture for MixedCriticality Systems. CRC Press, Taylor & Francis Incorporated.
13. M. A. Alam, K. Roy, and C. Augustine. 2011. Reliability and process-variation aware design of integrated circuits- A broader perspective. In Proceedings of the International Reliability Physics Symposium 4A.1.1-4A.1.11. DOI: https://doi.org/10.1109/IRPS.2011.5784500
14. S. Alcaide, L. Kosmidis, C. Hernandez, and J. Abella. 2019. High-integrity GPU designs for critical real-time automotive systems. In Proceedings of the Conference on Design, Automation & Test (DATE'19). 824-829. DOI:https://doi.org/10.23919/DATE.2019.8715177
15. I. Allende, N. Mc Guire, J. Perez, L. G. Monsalve, N. Uriarte, and Obermaisser R.2019. Towards Linux for the development of mixedCriticality embedded systems based on multiCore devices. In Proceedings of the 15th European Dependable Computing Conference (EDCC'19). 47-54. DOI:https://doi.org/10.1109/EDCC.2019.00020
16. B. Anuradha and C. Vivekanandan. 2012. Usage of scratchpad memory in embedded systems-State of art. In Proceedings of the 3rd International Conference on Computing, Communication, and Networking Technologies (ICCCNT'12). 1-5. DOI:https://doi.org/10.1109/ICCCNT.2012.6396100
17. J. Athavale, R. Mariani, and M. Paulitsch. 2019. Flight safety certification implications for complex multiCore processor based avionics systems. In Proceedings of the IEEE 25th International Symposium on On-Line Testing and Robust Syst. Design (IOLTS'19). 38-39. DOI:https://doi.org/10.1109/IOLTS.2019.8854415
18. A. Avizienis, J. C. Laprie, B. Randell, and C. Landwehr. 2004. Basic concepts and taxonomy of dependable and secure computing. In IEEE Transactions on Dependable and Secure Computing, Vol. 1.11-33.
19. A. Barros and L. M. Pinho. 2011. Software transactional memory as a building block for parallel embedded real-time systems. In Proceedings of the 37th Euromicro Conference on Software Engineering and Advanced Applications (SEAA). 251-255. DOI:https://doi.org/10.1109/SEAA.2011.46
20. H. Bauer, M. Patel, N. Santhanam, and B. Wiseman. 2015. McKinsey on Semiconductors. Technical Report.
21. C. Belwal and A. M. K. Cheng. 2011. Lazy versus eager conflict detection in software transactional memory: A realtime schedulability perspective. IEEE Embed. Syst. Lett. 3, 1 (2011), 37-41. DOI:https://doi.org/10.1109/LES.2010.2099104
22. Pedro Benedicte, Carles Hernandez, Jaume Abella, and Francisco J. Cazorla. 2018. HWP: Hardware support to reconcile cache energy, complexity, performance andWCET estimates in multicore real-time systems. In Proceedings of the 30th Euromicro Conference on Real-Time Systems (ECRTS'18). 3:1-3:22. DOI:https://doi.org/10.4230/LIPIcs.ECRTS. 2018.3
23. S. Bensalem, K. Goossens, C. M. Kirsch, R. Obermaisser, E. A. Lee, and J. Sifakis. 2011. Time-predictable and composable architectures for dependable embedded systems. In Proceedings of the 9th ACM International Conference on Embedded Software (EMSOFT'11). 351-352. DOI:https://doi.org/10.1145/2038642.2038697
24. C. Bernardeschi, L. Cassano, and A. Domenici. 2015. SRAM-based FPGA systems for safetyCritical applications: A survey on design standards and proposed methodologies. J.comput. Sci. Technol. 30, 2 (2015), 373-390. DOI:https://doi.org/10.1007/s11390-015-1530-5
25. A. Bilbao, I. Yarza, J. L. Montero, M. Azkarate-askasua, and N. Gonzalez. 2017. A railway safety and security concept for low-power mixedCriticality systems. In Proceedings of the IEEE 15th International Conference on Industrial Informatics (INDIN). 59-64. DOI:https://doi.org/10.1109/INDIN.2017.8104747
26. J. Bin. 2014. Controlling Execution Time Variability Using COTS for Safety Critical Systems. Thesis, Universite Paris-Sud.
27. J. Bin, S. Girbal, D. Gracia Perez, A. Grasset, and A. Merigot. 2014. Studying coRunning avionic real-time applications on multiCore COTS architectures. In Proceedings of the Embedded Real Time Software and Systems Conference
28. G. Blake, R. G. Dreslinski, and T. Mudge. 2009. A survey of multicore processors. IEEE Signal Process. Mag. 26, 6 (2009), 26-37. DOI:https://doi.org/10.1109/MSP.2009.934110
29. C. Bolchini, M. K. Michael, A. Miele, and S. Neophytou. 2018. Dependability Threats. Springer. DOI:https://doi.org/10.1007/978-3-319-54422-9
30. E. Bolotin, I. Cidon, R. Ginosar, and A. Kolodny. 2004. QNoC: QoS architecture and design process for network on chip. J. Syst. Archit. 50, 2-3 (2004), 105-128. DOI:https://doi.org/10.1016/j.sysarc.2003.07.004
31. C. Bradatsch, F. Kluge, and T. Ungerer. 2013. A cross-domain system architecture for embedded hard real-time manyCore systems. In Proceedings of the IEEE 10th International Conference on High Performance Computing and Communications (HPCC'13). 2034-2041. DOI:https://doi.org/10.1109/HPCC.and.EUC.2013.293
32. D. Bui, E. Lee, I. Liu, H. Patel, and J. Reineke. 2011. Temporal isolation on multiprocessing architectures. In Proceedings of the 48th ACM/EDAC/IEEE Design Automation Conference (DAC). 274-279.
33. A. Burns and R. I. David. 2018. A survey of research into mixed criticality systems. ACM Comput. Surv. 50, 6 (2018). DOI:https://doi.org/10.1145/3131347
34. A. Burns, J. Harbin, and L.S. Indrusiak. 2014. A wormhole NoC protocol for mixed criticality systems. In Proceedings of the IEEE Real-Time Syst. Symposium (RTSS'14). 184-195. DOI:https://doi.org/10.1109/RTSS.2014.13
35. D. Buttle. 2012. Real-Time in the Prime-Time-ECRTS Keynote Talk. Technical Report. ETAS Gmbh.
36. CAST. 2016. MultiCore Processors-Position Paper CAST-32A. Technical Report.
37. F. J. Cazorla, J. Abella, J. Andersson, T. Vardanega, F. Vatrinet, I. Bate, I. Broster, M. Azkarate-Askasua, F. Wartel, L. Cucu, F. Cros, G. Farrall, A. Gogonel, A. Gianarro, B. Triquet, C. Hernandez, C. Lo, C.Maxim,D.Morales, E.Quinones, E. Mezzetti, L. Kosmidis, I. Aguirre, M. Fernandez, M. Slijepcevic, P. Conmy, and W. Talaboulma. 2016. PROXIMA: Improving measurement-based timing analysis through randomisation and probabilistic analysis. In Proceedings of the Euromicro Conference on Digital Systems Design (DSD'16). 276-285. DOI:https://doi.org/10.1109/DSD.2016.22
38. F. J. Cazorla, L. Kosmidis, E. Mezzetti, C. Hernandez, J. Abella, and T. Vardanega. 2019. Probabilistic worstCase timing analysis: Taxonomy and comprehensive survey. ACM Comput. Surv. 52, 1 (2019). DOI:https://doi.org/10.1145/3301283
39. S. Chakraborty and S. Ramesh. 2015. Guest editorial special section on automotive embedded systems and software. IEEE Trans.comput.-Aided Design Integr. Circ. Syst. 34, 11 (2015), 1701-1703. DOI:https://doi.org/10.1109/TCAD. 2015.2488378
40. Jason A. Cheatham, John M. Emmert, and Stan Baumgart. 2006. A survey of fault tolerant methodologies for FPGAs. ACM Trans. Des. Autom. Electron. Syst.11, 2 (2006), 501-533. DOI:https://doi.org/10.1145/1142155.1142167
41. G. Corradi. 2017. Tools, architectures and trends on industrial all programmable heterogeneous MPSoC (KeyNote). In Proceedings of the 29th Euromicro Conference on Real-Time Systems (ECRTS'17).
42. A. Crespo, P. Balbastre, K. Chappuis, J. Coronel, J. Fanguede, P. Lucas, and J. Perez. 2018. Execution Environment. CRC Press.
43. A. Crespo, P. Balbastre, J. Sim, J. Coronel, D. Gracia Perez, and P. Bonnot. 2018. Hypervisor-based multicore feedback control of mixedCriticality systems. IEEE Access 6 (2018), 50627-50640.
44. N. Dagieu, A. Spyridakis, and D. Raho. 2016. Memguard: A memory bandwith management in mixed criticality virtualized systems memguard KVM scheduling. In Proceedings of the 10th International Conference on Mobile Ubiquitous Computing, Systems, Services, and Technologies (UBICOMM'16). Retrieved from https://www.thinkmind.org/index.phpview=article&articleid=ubicomm-2016-1-40-10072.
45. Shidhartha Das. 2009. Razor: A Variability-tolerant Design Methodology for Low-power and Robust Computing. Thesis, The University of Michigan.
46. S. Das. 2018. Variation-Mitigation for Reliable, Dependable and Energy-Efficient Future System Design. Springer. DOI:https://doi.org/10.1007/978-3-319-54422-9
47. D. Dasari, B. Akesson, V. Nelis, M. A. Awan, and S. M. Petters. 2013. Identifying the sources of unpredictability in COTS-based multicore systems. In Proceedings of the 8th IEEE International Symposium on Industrial Embedded Systems (SIES). 39-48. DOI:https://doi.org/10.1109/SIES.2013.6601469
48. D. Dasari and V. Nelis. 2012. An analysis of the impact of bus contention on theWCET inmulticores. In Proceedings of the IEEE 14th International Conference on High Performance Computing and Communications (HPCC'12). 1450-1457. DOI:https://doi.org/10.1109/HPCC.2012.212
49. M. Delvai,W.Huber, P. Puschner, and A. Steininger. 2003. Processor support for temporal predictability-The SPEAR design example. In Proceedings of the 15th Euromicro Conference on Real-Time Systems (ECRTS'03).
50. J. Diaz, C. Munoz Caro, and A. Nino. 2012. A survey of parallel programming models and tools in the multi and manyCore era. IEEE Trans. Parallel Distrib. Syst. 23, 8 (2012), 1369-1386. DOI:https://doi.org/10.1109/TPDS.2011.308
51. EASA. 2011. Development Assurance of Airborne Electronic Hardware. EASA CM-SWCEH-001, European Union Aviation Safety Agency (EASA). Retrieved from https://www.easa.europa.eu/sites/default/files/dfu/certificationdocs-certification-memorandum-EASACM-SWCEH-001-Development-Assurance-of-Airborne-Electronic-Hardware.pdf .
52. EASA. 2013. Certification Memorandum-Software Aspects of Certification-EASA. Technical Report.
53. L. Ecco, S. Tobuschat, S. Saidi, and R. Ernst. 2014. A mixed critical memory controller using bank privatization and fixed priority scheduling. In Proceedings of the IEEE 20th International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA'14). 1-10.DOI:https://doi.org/10.1109/RTCSA.2014.6910550
54. M. El-Shambakey and B. Ravindran. 2012. STM concurrency control for embedded real-time software with tighter time bounds. In Proceedings of the 49th Design Automation Conference (DAC'12). ACM, 437-446. DOI:https://doi.org/10.1145/2228360.2228437
55. EN 2011. EN50128-RailwayApplications: Communication, signalling and processing systems-Software for railway control and protection systems.
56. Meinhard Erben, Wolf Gunther, Tobias Sedlmeier, Dieter Lederer, and Klaus-Jurgen Amsler. 2006. Legal aspects of safety designed software development, especially under european law. In Proceedings of the 3rd European Embedded Real Time Software (ERTS'06). 6.
57. F. Eris, A. Joshi, A. B. Kahng, Y. Ma, S. Mojumder, and T. Zhang. 2018. Leveraging thermally-aware chiplet organization in 2.5D systems to reclaim dark silicon. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE'18). 1441-1446. DOI:https://doi.org/10.23919/DATE.2018.8342238
58. H. Esmaeilzadeh, E. Blem, R. St. Amant, K. Sankaralingam, and D. Burger. 2012. Dark silicon and the end of multicore scaling. IEEE Micro 32, 3 (2012), 122-134. DOI:https://doi.org/10.1109/MM.2012.17
59. M. Fakih, A. Lenz, M. Azkarate-Askasua, J. Coronel, A. Crespo, S. Davidmann, J. C. Diaz Garcia, N. Romero Gonzalez, K. Gruttner, S. Schreiner, R. Seyyedi, R. Obermaisser, A. Maleki, J. Oberg, M. T. Mohammadat, J. PerezCerrolaza, I. Sander, and I. Soderquist. 2017. SAFEPOWER project: Architecture for safe and power-efficient mixedCriticality systems. Microprocess. Microsyst. 52 (2017), 89-105. DOI:https://doi.org/10.1016/j.micpro.2017.05.016
60. G. Fernandez, J. Abella, E. Quinones, C. Rochange, T. Vardanega, and F. J. Cazorla. 2014. Contention in multicore hardware shared resources: Understanding of the state of the art. In Proceedings of the 14th International Workshop on WorstCase Execution Time Analysis, H. Falk (Ed.).31-42.
61. Gabriel Fernandez, Javier Jalle, Jaume Abella, Eduardo Quinones, Tullio Vardanega, and Francisco J. Cazorla. 2015. Increasing confidence on measurement-based contention bounds for real-time roundRobin buses. In Proceedings of the 52nd Design Automation Conference (DAC'15). ACM. DOI:https://doi.org/10.1145/2744769.2744858
62. S. Fisher. 2013. Certifying Applications in a MultiCore Environment: A New Approach Gains Success. Technical Report. SYSGO AG.
63. G. Furano and A. Menicucci. 2018. Roadmap for On-Board Processing and Data Handling Systems in Space. Springer. DOI:https://doi.org/10.1007/978-3-319-54422-9
64. R. Ginosar. 2012. Survey of processors for space. In Proceedings of the Conference on Data Systems In Aerospace (DASIA'12).
65. S. Girbal, X. Jean, J. Le Rhun, D. Gracia Perez, and M. Gatti. 2013. Deterministic platform software for hard real-time systems using multiCore COTS. In Proceedings of the IEEE/AIAA 32nd Digital Avionics Systems Conference (DASC'13). IEEE.
66. D. Gizopoulos, M. Psarakis, S. V. Adve, P. Ramachandran, S. K. S. Hari, D. Sorin, A. Meixner, A. Biswas, and X. Vera. 2011. Architectures for online error detection and recovery in multicore processors. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE'11). 1-6. DOI:https://doi.org/10.1109/DATE.2011.5763096
67. K. Goossens, A. Azevedo, K. Chandrasekar, M. D. Gomony, S. Goossens, M. Koedam, Y. Li, D. Mirzoyan, A. Molnos, A. B. Nejad, A. Nelson, and S. Sinha. 2013. Virtual execution platforms for mixed-timeCriticality systems: The Comp-SOC architecture and design flow. SIGBED Rev. 10, 3 (2013), 23-34. DOI:https://doi.org/10.1145/2544350.2544353
68. K. Goossens, J. Dielissen, and A. Radulescu. 2005. Aethereal network on chip: Concepts, architectures, and implementations. IEEE Design Test Comput. 22, 5 (2005), 414-421.
69. K. Goossens and A. Hansson. 2010.The aethereal network on chip after ten years: Goals, evolution, lessons, and future. In Proceedings of the 47th Design Automation Conference (DAC'10). ACM, 306-311. DOI:https://doi.org/10.1145/1837274.1837353
70. S. Goossens, B. Akesson, and K. Goossens. 2013. Conservative open policy for mixed timeCriticality memory controllers. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE'13). 525-530. DOI: https://doi.org/10.7873/DATE.2013.118
71. J. E. Gottschlich and D. A. Connors. 2008. Extending contention managers for user-defined priority-based transactions. In Proceedings of the Workshop on Exploiting Parallelism with Transactional Memory and other Hardware Assisted Methods (EPHAM'08).
72. Giovani Gracioli, Ahmed Alhammad, Renato Mancuso, Antonio Augusto Frohlich, and Rodolfo Pellizzoni. 2015. A survey on cache management mechanisms for real-time embedded systems. ACM Comput. Surv. 48, 2 (2015). DOI:https://doi.org/10.1145/2830555
73. E. Grade, A. Hayek, and J. Borcsok. 2016. Implementation of a fault-tolerant system using safetyRelated Xilinx tools conforming to the standard IEC 61508. In Proceedings of the International Conference on System Reliability and Science (ICSRS'16). 78-83. DOI:https://doi.org/10.1109/ICSRS.2016.7815842
74. P. Graydon and I. Bate. 2013. Safety assurance driven problem formulation for mixedCriticality scheduling. In Proceedings of the 1st International Workshop on Mixed Criticality Systems (WMC'13). 19-24.
75. Z. Gu and Q. Zhao. 2012. A state-of-The-art survey on real-time issues in embedded systems virtualization. J. Softw. Eng. Appl. 5, 1 (2012), 277-290. DOI:https://doi.org/10.4236/jsea.2012.54033
76. S. Guertin and M. White. 2010.CMOS reliability challenges-The future of commercial digital electronics and NASA. In Proceedings of the NEPP Electronics Technology Workshop.
77. E. Hallet, G. Corradi, and S. McNeil. 2015. WP461-Xilinx Reduces Risk and Increases Efficiency for IEC61508 and ISO26262 Certified Safety Applications. Technical Report. Xilinx.
78. J. Han, M. Deubzer, J. Seo Park, J. Harnisch, and P. Leteinturier. 2014. Efficient multiCore software design space exploration for hybrid control unit integration. In SAE Tech. Paper. DOI:https://doi.org/10.4271/2014-01-0260
79. A. Hayek and J. Borcsok. 2012. SRAM-based FPGA design techniques for safety related systems conforming to IEC 61508 a survey and analysis. In Proceedings of the 2nd International Conference on Advances in Computational Tools for Engineering Applications (ACTEA).319-324. DOI:https://doi.org/10.1109/ICTEA.2012.6462892
80. A. Hayek and J. Borcsok. 2014. Safety chips in light of the standard IEC 61508: Survey and analysis. In Proceedings of the International Symposium on Fundamentals of Electrical Engineering (ISFEE'14). 1-6. DOI:https://doi.org/10.1109/ISFEE.2014.7050579
81. A. Hayek, B. Machmur, M. Schreiber, J. Borcsok, S. Golz, and M. Epp. 2014. HICore1: Safety on a chip; turnkey solution for industrial control. In Proceedings of the IEEE 25th International Conference on Application-Specific Systems, Architectures, and Processors (ASAP'14). 74-75. DOI:https://doi.org/10.1109/ASAP.2014.6868636
82. A. Hayek, M. Schreiber, B. Machmur, and J. Borcsok. 2013. Design and implementation of onChip safety controller in terms of the standard IEC 61508. In Proceedings of the Conference on Recent Advances in Circuits; Systems and Automatic Control.
83. J. Henkel, L. Bauer, N. Dutt, P. Gupta, S. Nassif, M. Shafique, M. Tahoori, and N.Wehn. 2013. Reliable onChip systems in the nano-era: Lessons learnt and future trends. In Proceedings of the 50th ACM/EDAC/IEEE Design Automation Conference (DAC'13). 1-10.DOI:https://doi.org/10.1145/2463209.2488857
84. Carles Hernandez, Jaume Abella, Francisco J. Cazorla, Alen Bardizbanyan, Jan Andersson, Fabrice Cros, and Franck Wartel. 2017. Design and implementation of a time predictable processor: Evaluation with a space case study. In Proceedings of the 29th Euromicro Conference on Real-Time Systems (ECRTS'17), Vol. 76. 16:1-16:23. DOI:https://doi.org/10.4230/LIPIcs.ECRTS.2017.16
85. S. Hesham, J. Rettkowski, D. Goehringer, and M. A. Abd El Ghany. 2017. Survey on real-time networks-onChip. IEEE Trans. Parallel Distrib. Syst. 28, 5 (2017), 1500-1517. DOI:https://doi.org/10.1109/TPDS.2016.2623619
86. Salma Hesham, Jens Rettkowski, Diana Gohringer, and Mohamed A. Abd El Ghany. 2015. Survey on real-time network-onChip architectures. In Applied Reconfigurable Computing, Kentaro Sano,Dimitrios Soudris, MichaelHubner, and Pedro C. Diniz (Eds.). Springer, Cham, 191-202.
87. C. Hilton and B. Nelson. 2006. PNoC: A flexible circuit-switched NoC for FPGA-based systems. IEEE Proc.comput. Dig. Techn. 153, 3 (2006), 181-188. DOI:https://doi.org/10.1049/ipCdt:20050175
88. P. Huyck. 2012. ARINC 653 and multiCore microprocessors-Considerations and potential impacts. In Proceedings of the IEEE/AIAA 31st Digital Avionics Systems Conference (DASC'12). 6B41-6B47.
89. IEC 2010.IEC 61508(-1/7): Functional safety of electrical/electronic/programmable electronic safetyRelated systems. Technical Report.
90. IEC 2018. IEC 62443-4-1: Security for industrial automation and control systems-Part 4-1: Secure product development lifecycle requirements. Technical Report.
91. Infineon. 2018. AURIX 32-bit Microcontrollers for Automotive and Industrial Applications. Technical Report. Infineon.
92. C. Iordanou, V. Soteriou, and K. Aisopos. 2014. Hermes: Architecting a top-performing fault-tolerant routing algorithm for networks-onChips. In Proceedings of the IEEE 32nd International Conference on Computer Design (ICCD'14). 424-431. DOI:https://doi.org/10.1109/ICCD.2014.6974715
93. ISO 2018. ISO 26262(-1/11) Road vehicles-Functional safety. Technical Report.
94. ITRS. 2018. International Roadmap for Devices and Systems-Executive Summary. Technical Report. IEEE.
95. X. Iturbe, B. Venu, J. Jagst, E. Ozer, P. Harrod, C. Turner, and J. Penton. 2018. Addressing functional safety challenges in autonomous vehicles with the Arm TCLS architecture. IEEE Design Test 35, 3 (2018), 7-14. DOI:https://doi.org/10.1109/MDAT.2018.2799799
96. V. Izosimov, A. Paschalis, P. Reviriego, and H. Manhaeve. 2018. Application-Specific Solutions. Springer. DOI: https://doi.org/10.1007/978-3-319-54422-9
97. J. Jalle, E. Quinones, J. Abella, L. Fossati, M. Zulianello, and F. J. Cazorla. 2014. A dualCriticality memory controller (DCmc): Proposal and evaluation of a space case study. In Proceedings of the IEEE Real-Time Systems Symposium (RTSS'14). 207-217. DOI:https://doi.org/10.1109/RTSS.2014.23
98. X. Jean. 2015. Hypervisor Control of COTS MultiCores Processors in Order to Enforce Determinism for Future Avionics Equipment. Ph.D. Dissertation. Telecom ParisTech.
99. X. Jean, M. Gatti, G. Berthon, and M. Fumey. 2011. The Use of Multicore Processors in Airborne Systems (EASA 2011.C31). Technical Report. EASA, Thales Avionics.
100. S. K. Jena and M. B. Srinivas. 2012. On the suitability of multiCore processing for embedded automotive systems. In Proceedings of the International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery (CyberC'12).315-322. DOI:https://doi.org/10.1109/CyberC.2012.60
101. R. Kalayappan and S. R. Sarangi. 2013. A survey of checker architectures. ACM Comput. Surv. 45, 4 (2013), 1-34. DOI:https://doi.org/10.1145/2501654.2501662
102. B. Keller, M. Cochet, B. Zimmer, J. Kwak, A. Puggelli, Y. Lee, M. Blagojevi, S. Bailey, P. F. Chiu, P. Dabbelt, C. Schmidt, E. Alon, K. Asanovi, and B. Nikoli. 2017. A RISC-V processor SoC with integrated power management at submicrosecond timescales in 28 nm FD-SOI. IEEE J. Solid-State Circ. 52, 7 (2017), 1863-1875. DOI:https://doi.org/10.1109/JSSC.2017.2690859
103. S. Kiamehr, M. B. Tahoori, and L. Anghel. 2018. Manufacturing Threats. Springer. DOI:https://doi.org/10.1007/978-3-319-54422-9
104. L. M. Kinnan. 2009. Use of multicore processors in avionics and its potential impact on implementation and certification. SAE Tech. Papers (2009).
105. Hermann Kopetz. 2019. Simplicity is Complex: Foundations of Cyber-Physical System Design. Springer. DOI:https://doi.org/10.1007/978-3-030-20411-2
106. Leonidas Kosmidis, Jerome Lachaize, Jaume Abella, Olivier Notebaert, Francisco J. Cazorla, and David Steenari. 2019. GPU4S: Embedded GPUs in space. In Proceedings of the 22nd Euromicro Conference on Digital Systems Design (DSD'19).
107. O. Kotaba, J. Nowotsch, M. Paulitsch, S. M. Petters, and H. Theilingx. 2013. Multicore in real-time systems-Temporal isolation challenges due to shared resources. In Proceedings of theWorkshop on Industry-Driven Approaches for Costeffective Certification of SafetyCritical, MixedCriticality Systems (WICERT'13).
108. S. Kriaa, L. PietreCambacedes, M. Bouissou, and Y. Halgand. 2015. A survey of approaches combining safety and security for industrial control systems. Rel. Eng. Syst. Safety 139 (2015), 156-178.
109. K. Lakshmanan, S. Kato, and R. Rajkumar. 2010.Scheduling parallel real-time tasks on multiCore processors. In Proceedings of the 31st IEEE Real-Time Systems Symposium 259-268. DOI:https://doi.org/10.1109/RTSS.2010.42
110. A. Larrucea, I. Agirre, C. F. Nicolas, J. Perez, M. Azkarate-Askasua, and T. Trapman. 2015. Temporal independence validation of an IEC-61508 compliant mixedCriticality system based on multicore partitioning. In Proceedings of the Forum on Specification and Design Languages (FDL'15). 1-8.
111. A. Larrucea, I. Martinez, H. Ahmadian, R. Obermaisser, V. Brocal, S. Peiro, and J. Perez. 2016. DREAMS: Crossdomain mixedCriticality patterns. In Proceedings of the MixedCriticality Workshop on Real Time System Symposium (RTSS'16).
112. A. Larrucea, I. Martinez, R. Obermaisser, J. Perez, and C. F. Nicolas. 2017. Modular development of dependablemixedcriticality embedded systems. In Proceedings of the 20th Euromicro Conference on Digital Systems Design (DSD'17). 419-426. DOI:https://doi.org/10.1109/DSD.2017.93
113. A. Larrucea, J. Perez, I. Agirre, V. Brocal, and R. Obermaisser. 2015. Amodular safety case for an IEC 61508 compliant generic hypervisor. In Proceedings of the 18th Euromicro Conference on Digital Systems Design (DSD'15). 571-574. DOI:https://doi.org/10.1109/DSD.2015.27
114. A. Larrucea, J. Perez, and R. Obermaisser. 2015. A modular safety case for an IEC 61508 compliant COTS multicore device. In Proceedings of the 13th International Conference on Dependable, Autonomatic and Secure Computing (DASC'15). 8. DOI:https://doi.org/10.1109/DSD.2016.66
115. A. Larrucea, J. Perez, and R. Obermaisser. 2015. A modular safety case for an IEC 61508 compliant generic COTS processor. In Proceedings of the IEEE International Conference on Computing and Information Technology; Ubiquitous Computing and Communication; Dependable, Autonomic and Secure Computing; Pervasive Intellegence and Computing (CIT/IUCC/DASC/PICom'15). 1788-1795. DOI:https://doi.org/10.1109/CIT/IUCC/DASC/PICOM.2015.269
116. E. A. Lee. 2008. Cyber physical systems: Design challenges. In Proceedings of the 11th IEEE International Symposium on Object Oriented Real-Time Distributed Computing (ISORC'08). 363-369.
117. Ikhwan Lee, Michael Sullivan, Evgeni Krimer, DongWan Kim, Mehmet Basoglu, Doe Hyun Yoon, Larry Kaplan, and Mattan Erez. 2012. Survey of Error and Fault Detection Mechanisms. Technical Report. The University of Texas. Retrieved from http://lph.ece.utexas.edu/merez/uploads/MattanErez/detection-mechanisms-TR-LPH-2011-002.pdf.
118. P. Leteinturier, S. Brewerton, and K. Scheibert. 2008. MultiCore benefits & challenges for automotive applications. In SAE Tech. Paper. DOI:https://doi.org/10.4271/2008-01-0989
119. Paul S. Levy. 2017. WP495-Using Zynq-7000 SoC IEC 61508 Artifacts to Achieve ISO 13849 Compliance. Technical Report. Xilinx.
120. Y. Li, B. Akesson, and K. Goossens. 2014. Dynamic command scheduling for real-time memory controllers. In Proceedings of the 26th Euromicro Conference on Real-Time Systems (ECRTS'14). 3-14. DOI:https://doi.org/10.1109/ECRTS.2014.18
121. I. Liu, J. Reineke, D. Broman, M. Zimmer, and E. A. Lee. 2012. A PRET microarchitecture implementation with repeatable timing and competitive performance. In Proceedings of the IEEE 30th International Conference on Computer Design (ICCD'12). 87-93. DOI:https://doi.org/10.1109/ICCD.2012.6378622
122. I. Liu, J. Reineke, and E. A. Lee. 2010.A PRET architecture supporting concurrent programs with composable timing properties. In Proceedings of the 44th Asilomar Conference on Signals, Systems, and Computing (ASILOMAR'10). 2111-2115. DOI:https://doi.org/10.1109/ACSSC.2010.5757922
123. A. Lofwenmark and S. Nadjm-Tehrani. 2018. Fault and timing analysis in critical multiCore systems: A survey with an avionics perspective. J. Syst. Architect. 87 (2018), 1-11. DOI:https://doi.org/10.1016/j.sysarc.2018.04.001
124. H. Lu. 2013. LowCost Highly-Efficient Fault Tolerant Processor Design for Mitigating the Reliability Issues in Nanometric Technologies. Thesis, Universite de Grenoble.
125. G. Macher, M. Bachinger, and M. Stolz. 2017. Embedded multiCore system for design of next-generation powertrain control units. In Proceedings of the 13th European Dependable Computing Conference (EDCC'17). 66-72. DOI:https://doi.org/10.1109/EDCC.2017.32
126. G. Macher, A. Holler, E. Armengaud, and C. Kreiner. 2015. Automotive embedded software: Migration challenges to multiCore computing platforms. In Proceedings of the IEEE 13th International Conference on Industrial Informatics (INDIN'15). 1386-1393. DOI:https://doi.org/10.1109/INDIN.2015.7281937
127. A. Maheshwari, W. Burleson, and R. Tessier. 2004. Trading off transient fault tolerance and power consumption in deep submicron (DSM) VLSI circuits. IEEE Trans. Very Large Scale Integr. Syst. 12, 3 (2004), 299-311. DOI:https://doi.org/10.1109/TVLSI.2004.824302
128. Claire Maiza, Hamza Rihani, Juan M. Rivas, Joel Goossens, Sebastian Altmeyer, and Robert I. Davis. 2019. A survey of timing verification techniques for multiCore real-time systems. ACM Comput. Surv. 52, 3 (2019). DOI:https://doi.org/10.1145/3323212
129. R. Mariani, G. Boschi, and F. Colucci. 2007. Using an innovative SoC-level FMEA methodology to design in compliance with IEC 61508. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE'07). 1-6. DOI:https://doi.org/10.1109/DATE.2007.364641
130. Arya Mazaheri, Johannes Schulte, Matthew Moskewicz, Felix Wolf, and Ali Jannesari. 2019. Enhancing the programmability and performance portability of GPU tensor operations. In Proceedings of the 25th Euro-Par Conference (Lecture Notes in Computer Science), Vol.11725. Springer, 213-226. DOI:https://doi.org/10.1007/978-3-030-29400-7-16
131. A. Meixner, M. E. Bauer, and D. Sorin. 2007. Argus: LowCost, comprehensive error detection in simple cores. In Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'07). 210-222. DOI:https://doi.org/10.1109/MICRO.2007.18
132. S. Metzlaff, S. Weis, and T. Ungerer. 2013. Leveraging transactional memory for a predictable execution of applications composed of hard real-time and best-effort tasks. In Proceedings of the 21st International Conference on Real-Time Networks and Systems (RTNS'13). ACM, 45-54. DOI:https://doi.org/10.1145/2516821.2516832
133. M. Millberg, E. Nilsson, R. Thid, and A. Jantsch. 2004. Guaranteed bandwidth using looped containers in temporally disjoint networks within the nostrum network on chip. In Proceeding of the Conference on Design, Automation and Test in Europe (DATE'04), Vol. 2. 890-895.
134. T. Mitra, J. Teich, and L. Thiele. 2018. TimeCritical systems design: A survey. IEEE Design Test 35, 2 (2018), 8-26. DOI:https://doi.org/10.1109/MDAT.2018.2794204
135. S. Mittal. 2016. A survey of recent prefetching techniques for processor caches. ACM Comput. Surv. 49, 2 (2016). DOI:https://doi.org/10.1145/2907071
136. S. Mittal. 2017. A survey of techniques for cache partitioning in multicore processors. ACM Comput. Surv. 50, 2 (2017). DOI:https://doi.org/10.1145/3062394
137. Sparsh Mittal and Jeffrey S. Vetter. 2015. A survey of CPU-GPU heterogeneous computing techniques. ACM Comput. Surv. 47, 4 (2015). DOI:https://doi.org/10.1145/2788396
138. S. R. Msirdi. 2017. Modular Avionics Software Integration on MultiCore COTS: CertificationCompliant Methodology and Timing Analysis Metrics for Legacy Software Reuse in Modern Aerospace Systems. Thesis, Universite de Toulouse.
139. Imanol Mugarza, Jorge Parra, and Eduardo Jacob. 2017. Software updates in safety and security co-engineering. In Computer Safety, Reliability, and Security, Stefano Tonetta, Erwin Schoitsch, and Friedemann Bitsch (Eds.). Springer, Cham, 199-210.
140. H. Mushtaq, Z. Al-Ars, and K. Bertels. 2015. Calculation of worstCase execution time for multicore processors using deterministic execution. In Proceedings of the 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS'15). 33-39. DOI:https://doi.org/10.1109/PATMOS.2015.7347584
141. G. Nelissen, D. Pereira, and L. M. Pinho. 2015. A novel run-time monitoring architecture for safe and efficient inline monitoring. In Reliable Software Technologies-Ada-Europe, Juan Antonio de la Puente and Tullio Vardanega (Eds.). Springer, 66-82.
142. T. S. Nidhin, Anindya Bhattacharyya, R. P. Behera, and T. Jayanthi. 2018. A review on SEU mitigation techniques for FPGA configuration memory. IETE Tech. Rev. 35, 2 (2018), 157-168. DOI:https://doi.org/10.1080/02564602.2016. 1265905
143. J. Nowotsch and M. Paulitsch. 2012. Leveraging multiCore computing architectures in avionics. In Proceedings of the 9th European Dependable Computing Conference (EDCC'12). 132-143.
144. R. Obermaisser, C. El Salloum, B. Huber, and H. Kopetz. 2008. The time-triggered system-on-aChip architecture. In Proceedings of the IEEE International Symposium on Industrial Electronics (ISIE'08). 1941-1947. DOI:https://doi.org/10.1109/ISIE.2008.4677135
145. R. Obermaisser, C. El Salloum, B. Huber, and H. Kopetz. 2009. From a federated to an integrated automotive architecture. IEEE Trans.comput.-Aided Design Integr. Circ. Syst. 28, 7 (2009), 956-965. DOI:https://doi.org/10.1109/TCAD. 2009.2014005
146. M. Ottavi, D. Gizopoulos, and S. Pontarelli. 2018. Dependable Multicore Architectures at Nanoscale. Springer. DOI:https://doi.org/10.1007/978-3-319-54422-9
147. M. Ottavi, S. Pontarelli, D. Gizopoulos, C. Bolchini, M. K. Michael, L. Anghel, M. Tahoori, A. Paschalis, P. Reviriego, O. Bringmann, V. Izosimov, H. Manhaeve, C. Strydis, and S. Hamdioui. 2015. Dependable multicore architectures at nanoscale: The view from europe. IEEE Design Test 32, 2 (2015), 17-28. DOI:https://doi.org/10.1109/MDAT.2014. 2359572
148. Z. Owda and R. Obermaisser. 2017. MixedCriticality transactional memory controller for embedded systems. In IEEE International Conference on Industrial Informatics (INDIN'17). 104-110.DOI:https://doi.org/10.1109/INDIN.2016. 7819142
149. I. Oz and S. Arslan. 2019. A survey on multithreading alternatives for soft error fault tolerance. ACM Comput. Surv. 52, 2 (2019), 1-38. DOI:https://doi.org/10.1145/3302255
150. Haluk Ozaktas, Christine Rochange, and Pascal Sainrat. 2013. AutomaticWCET analysis of real-time parallel applications. In Proceedings of the 13th International Workshop on WorstCase Execution Time Analysis (WCET'13).
151. Milos Pani, Sebastian Kehr, Eduardo Quinones, Bert Boddecker, Jaume Abella, and Francisco J. Cazorla. 2014. Run-Par: An allocation algorithm for automotive applications exploiting runnable parallelism in multicores. In Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES'14). ACM, Article 29, 10 pages. DOI:https://doi.org/10.1145/2656075.2656096
152. M. Paolieri, J. Mische, S. Metzlaff, M. Gerdes, E. Quinones, S. Uhrig, T. Ungerer, and F. J. Cazorla. 2013. A hard realtime capable multiCore SMT processor. ACM Trans. Embed.comput. Syst. 12, 3 (2013). DOI:https://doi.org/10.1145/2442116.2442129
153. M. Paolieri, E. Quinones, F. J. Cazorla, and M. Valero. 2009. An analyzable memory controller for hard real-time CMPs. IEEE Embed. Syst. Lett. 1, 4 (2009), 86-90. DOI:https://doi.org/10.1109/LES.2010.2041634
154. C. Paukovits. 2008. The Time-triggered System-onChip Architecture. Thesis. Institut fur Technische Informatik.
155. M. Paulitsch, O. M. Duarte, H. Karray, K. Mueller, D. Muench, and J. Nowotsch. 2015. MixedCriticality embedded systems-A balance ensuring partitioning and performance. In Proceedings of the Euromicro Conference on Digital System Design (DSD'15). 453-461. DOI:https://doi.org/10.1109/DSD.2015.100
156. R. Pellizzoni, A. Schranzhofer, Chen Jian-Jia, M. Caccamo, and L. Thiele. 2010.Worst case delay analysis for memory interference in multicore systems. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE'10). 741-746. DOI:https://doi.org/10.1109/DATE.2010.5456952
157. J. Perez, M. Coppola, M. Faugere, D. Gracia Perez, M. Grammatikakis, A. Larrucea Ortube, A. Mouzakitis, A. Papagrigoriou, P. Petrakis, V. Piperaki, I. Sarasola, and G. Tsamis. 2018. Evaluation. CRC Press.
158. J. Perez, D. Gonzalez, C. F. Nicolas, T. Trapman, and J. M. Garate. 2014. A safety certification strategy for IEC-61508 compliant industrial mixedCriticality systems based on multicore partitioning. In Proceedings of the 17th Euromicro Conference on Digital Syst. Design (DSD'14). 394-400. DOI:https://doi.org/10.1109/DSD.2014.38
159. J. Perez, D. Gonzalez, S. Trujillo, and A. Trapman. 2015. A Safety Concept for an IEC 61508 Compliant Fail-safe Wind Power MixedCriticality Embedded System Based on MultiCore Partitioning. Lecture Notes in Computer Science, Vol. 9111. Springer. 3-17. DOI:https://doi.org/10.1007/978-3-319-19584-1-1
160. S. Pinto, A. Oliveira, J. Pereira, J. Cabral, J. Monteiro, and A. Tavares. 2017. Lightweight multicore virtualization architecture exploiting ARM TrustZone. In Proceedings of the 43rd IEEE Industrial Electronics Society (IECON'17). 3562-3567. DOI:https://doi.org/10.1109/IECON.2017.8216603
161. A. Platschek, N. Mc Guire, and L. Bulwahn. 2018. Certifying Linux: Lessons learned in three years of SIL2LinuxMP. In Proceedings of the Embedded World Conference.
162. S. Pontarelli, Juan A. Maestro, and P. Reviriego. 2018. Dependability Solutions. Springer. DOI:https://doi.org/10.1007/978-3-319-54422-9
163. B. Krishna Priya, Amit D. Joshi, and N. Ramasubramanian. 2016. A survey on performance of onChip cache for multiCore architectures. In Proceedings of the International Conference on Informatics and Analytics (ICIA'16). ACM. DOI:https://doi.org/10.1145/2980258.2980336
164. Roger Pujol, Hamid Tabani, Leonidas Kosmidis, Enrico Mezzetti, Jaume Abella, and Francisco J. Cazorla. 2019. Generating and exploiting deep learning variants to increase heterogeneous resource utilization in the NVIDIA Xavier. In Proceedings of the 31st Euromicro Conference on Real-Time Systems (ECRTS'19) (Leibniz International Proceedings in Informatics (LIPIcs)), Sophie Quinton (Ed.), Vol. 133. Schloss Dagstuhl-Leibniz-Zentrum fuer Informatik, Dagstuhl, Germany, 23:1-23:23. DOI:https://doi.org/10.4230/LIPIcs.ECRTS.2019.23
165. P. Puschner. 2013. Embedded systems for safetyCritical and mixedCriticality applications. In Proceedings of the 2nd Mediterranean Conference on Embedded Computers (MECO'13). 1-2.
166. P. Puschner, B. Cilku, and D. Prokesch. 2016. Constructing time-predictable MPSoCs: Avoid conflicts in temporal control. In Proceedings of the IEEE 10th International Symposium on Embedded Multicore/ManyCore Systems-onChip (MCSOC'16). 321-328. DOI:https://doi.org/10.1109/MCSoC.2016.55
167. Arthur Pyka, Mathias Rohde, and Sascha Uhrig. 2014. A real-time capable coherent data cache for multicores. Concurr.comput.: Pract. Exper. 26, 6 (2014), 1342-1354.
168. Eduardo Quinones, Marko Bertogna, Erez Hadad, Ana Juan Ferrer, Luca Chiantore, and Alfredo Reboa. 2018. Big data analytics for smart cities: The H2020 CLASS project. In Proceedings of the 11th ACM International Systems and Storage Conference (SYSTOR'18). ACM, 130. DOI:https://doi.org/10.1145/3211890.3211914
169. S. Royuela, A. Duran, M. A. Serrano, E. Quinones, and X. Martorell. 2017. A Functional Safety OpenMP for Critical Real-Time Embedded Systems. Springer, Book section 16. DOI:https://doi.org/10.1007/978-3-319-65578-9-16
170. S. Saidi, R. Ernst, S. Uhrig, H. Theiling, and B. D. de Dinechin. 2015. The shift to multicores in real-time and safetycritical systems. In Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis. IEEE Press, 220-229. DOI:https://doi.org/10.1109/CODESISSS.2015.7331385
171. O. Sander, F. Bapp, L. Dieudonne, T. Sandmann, and J. Becker. 2017. The promised future of multiCore processors in avionics systems. CEAS Aeronaut. J. 8, 1 (2017), 143-155. DOI:https://doi.org/10.1007/s13272-016-0228-x
172. I. Schagaev and T. Kaegi-Trachsel. 2016. Software Design for Resilient Computer Systems. Springer. DOI:https://doi.org/10.1007/978-3-319-29465-0
173. K. Schmidt, J. Harnisch, D. Marx, A. Mayer, A. Kohn, and R. Deml. 2014. Timing analysis and tracing concepts for ECU development. SAE World Congr. Exhibit. 1 (2014). DOI:https://doi.org/10.4271/2014-01-0190
174. M. Schoeberl, S. Abbaspour, B. Akesson, N. Audsley, R. Capasso, J. Garside, K. Goossens, S. Goossens, S. Hansen, R. Heckmann, S. Hepp, B. Huber, A. Jordan, E. Kasapaki, J. Knoop, Y. Li, D. Prokesch, W. Puffitsch, P. Puschner, A. Rocha, C. Silva, J. Sparso, and A. Tocchi. 2015. TCREST: Time-predictable multiCore architecture for embedded systems. J. Syst. Architect. 61, 9 (2015), 449-471. DOI:https://doi.org/10.1016/j.sysarc.2015.04.002
175. M. Schoeberl, W. Puffitsch, S. Hepp, B. Huber, and D. Prokesch. 2018. Patmos: A time-predictable microprocessor. Real-Time Syst. 54, 2 (2018), 389-423. DOI:https://doi.org/10.1007/s11241-018-9300-4
176. Erwin Schoitsch. 2013. D6.1-State of the Art for System Qualification and Certification, V&V Survey (EMC2). Technical Report.
177. A. Scolari, F. Sironi, D. Sciuto, and M. D. Santambrogio. 2014. A survey on recent hardware and software-level cache management techniques. In Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications.242-247. DOI:https://doi.org/10.1109/ISPA.2014.41
178. Maria A. Serrano, Sara Royuela, and Eduardo Quinones. 2018. Towards an OpenMP specification for critical realtime systems. In Proceedings of the 14th International Workshop on OpenMP (IWOMP'18). 143-159. DOI:https://doi.org/10.1007/978-3-319-98521-3-10
179. Z. Shi and A. Burns. 2008. Real-time communication analysis for onChip networks with wormhole switching. In Proceedings of the 2nd ACM/IEEE International Symposium on Networks-onChip (NOCS'08). 161-170. DOI:https://doi.org/10.1109/NOCS.2008.4492735
180. M. Slijepcevic, L. Kosmidis, J. Abella, E. Quinones, and F. J. Cazorla. 2014. Timing verification of fault-tolerant chips for safetyCritical applications in harsh environments. IEEE Micro 34, 6 (2014), 8-19. DOI:https://doi.org/10.1109/MM.2014.59
181. Daniel J. Sorin. 2009. Fault Tolerant Computer Architecture. Morgan & Claypool Publishers. DOI:https://doi.org/10.2200/S00192ED1V01Y200904CAC005
182. V. Sridharan and S. Gurumurthi. 2018. Resilience Proportionality-A Paradigm for Efficient and Reliable System Design. Springer. DOI:https://doi.org/10.1007/978-3-319-54422-9
183. H. Sutter and J. Larus. 2005. Software and the concurrency revolution. Queue 3, 7 (2005), 54-62. DOI:https://doi.org/10.1145/1095408.1095421
184. S. Trujillo, A. Crespo, A. Alonso, and J. Perez. 2014. MultiPARTES: MultiCore partitioning and virtualization for easing the certification of mixedCriticality systems. Microprocess. Microsyst. 38, 8, Part B (2014), 921-932. DOI: https://doi.org/10.1016/j.micpro.2014.09.004
185. G. Tsamis, S. Kavvadias, A. Papagrigoriou, M. D. Grammatikakis, and K. Papadimitriou. 2016. Efficient bandwidth regulation at memory controller formixed criticality applications. In Proceedings of the 11th International Symposium on Reconfigurable CommunicationCentric Systems-onChip (ReCoSoC'16). 1-8. DOI:https://doi.org/10.1109/ReCoSoC. 2016.7533902
186. Theo Ungerer, Christian Bradatsch, Martin Frieb, Florian Kluge, Jorg Mische, Alexander Stegmeier, Ralf Jahr, Mike Gerdes, Pavel Zaykov, Lucie Matusova, Zai Jian Jia Li, Zlatko Petrov, Bert Boddeker, Sebastian Kehr, Hans Regler, Andreas Hugl, Christine Rochange, Haluk Ozaktas, Hugues Casse, Armelle Bonenfant, Pascal Sainrat, Nick Lay, David George, Ian Broster, Eduardo Quinones, Milos Panic, Jaume Abella, Carles Hernandez, Francisco Cazorla, Sascha Uhrig, Mathias Rohde, and Arthur Pyka. 2016. Parallelizing industrial hard real-time applications for the parMERASA multicore. ACM Trans. Embed.comput. Syst. 15, 3 (2016). DOI:https://doi.org/10.1145/2910589
187. A. Vajda. 2011. MultiCore and ManyCore Processor Architectures. Springer US, Boston, MA, 9-43. DOI:https://doi.org/10.1007/978-1-4419-9739-5-2
188. P. K. Valsan, H. Yun, and F. Farshchi. 2016. Taming non-blocking caches to improve isolation in multicore real-time systems. In Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS'16). 1-12. DOI:https://doi.org/10.1109/RTAS.2016.7461361
189. F. Wartel, L. Kosmidis, A. Gogonel, A. Baldovino, Z. Stephenson, B. Triquet, E. Quinones, C. Lo, E. Mezzetta, I. Broster, J. Abella, L. Cucu-Grosjean, T. Vardanega, and F. J. Cazorla. 2015. Timing analysis of an avionics case study on complex hardware/software platforms. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE'15). 397-402. DOI:https://doi.org/10.7873/DATE.2015.0189
190. F. Wartel, L. Kosmidis, C. Lo, B. Triquet, E. Quinones, J. Abella, A. Gogonel, A. Baldovin, E. Mezzetti, L. Cucu, T. Vardanega, and F. J. Cazorla. 2013. Measurement-based probabilistic timing analysis: Lessons from an integratedmodular avionics case study. In Proceedings of the 8th IEEE International Symposium on Industrial Embedded Systems (SIES'13). 241-248. DOI:https://doi.org/10.1109/SIES.2013.6601497
191. Saud Wasly. 2018. Architecture Design for Distributed MixedCriticality Systems Based on MultiCore Chips. Thesis, Universitat Siegen.
192. Raphael Weber. 2019. ARAMIS II. Tool interoperability and exchange formats. In Proceedings of the International Workshop on Automated Engineering of Autonomic and Run-time Evolving Systems. Final Workshop, Stuttgart.
193. W. Weber, A. Hoess, J. v. Deventer, F. Oppenheimer, R. Ernst, A. Kostrzewa, P. Dore, T. Goubier, H. Isakovic, N. Druml, E. Wuchner, D. Schneider, E. Schoitsch, E. Armengaud, T. Soderqvist, M. Traversone, S. Uhrig, J. C. Perez-Cortes, S. Saez, J. Kuusela, M. v. Helvoort, X. Cai, B. Nordmoen, G. Y. Paulsen, H. P. Dahle, M. Geissel, J. Salecker, and P. Tummeltshammer. 2016. The EMC2 project on embedded microcontrollers: Technical progress after two years. In Proceedings of the Euromicro Conference on Digital Systems Design (DSD'16). 524-531. DOI:https://doi.org/10.1109/DSD.2016.72
194. D. Wentzlaff, P. Griffin, H. Hoffmann, L. Bao, B. Edwards, C. Ramey, M. Mattina, C. C. Miao, J. F. Brown III, and A. Agarwal. 2007. OnChip interconnection architecture of the tile processor. IEEE Micro 27, 5 (2007), 15-31. DOI:https://doi.org/10.1109/MM.2007.4378780
195. R. Wilhelm, J. Engblom, A. Ermedahl, N. Holsti, S. Thesing, D. Whalley, G. Bernat, C. Ferdinand, R. Heckmann, T. Mitra, F. Mueller, I. Puaut, P. Puschner, J. Staschulat, and P. Stenstr. 2008. The worstCase execution-time problem- Overview of methods and survey of tools. ACM Trans. Embed.comput. Syst. 7, 3 (2008), 1-53. DOI:https://doi.org/10.1145/1347375.1347389
196. J. Windsor, K. Eckstein, P. Mendham, and T. Pareaud. 2011. Time and space partitioning security components for spacecraft flight software. In Proceedings of the 30th IEEE/AIAA Digital Avionics Systems Conference (DASC'11). 8A5-1-8A5-14. DOI:https://doi.org/10.1109/DASC.2011.6096140
197. W. Wolf, A. A. Jerraya, and G. Martin. 2008. Multiprocessor system-onChip (MPSoC) technology. IEEE Trans.comput.-Aided Design Integr. Circ. Syst. 27, 10 (2008), 1701-1713. DOI:https://doi.org/10.1109/TCAD.2008.923415
198. Xilinx. 2018. UG1085-Zynq UltraScale+ Device-Technical Reference Manual. Technical Report. Xilinx.
199. Xilinx. 2018. UG116-Device Reliability Report-First Half 2018. Technical Report. Xilinx.
200. H. Yun. 2013. Improving Real-Time Performance on Multicore Platforms Using MemGuard. Retrieved from http://www.ittc.ku.edu/%7Eheechul/papers/memguardRtlws13.pdf.
201. H. Yun, G. Yao, R. Pellizzoni, M. Caccamo, and L. Sha. 2013. MemGuard: Memory bandwidth reservation system for efficient performance isolation in multiCore platforms. In Proceedings of the IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS'13). 55-64. DOI:https://doi.org/10.1109/RTAS.2013.6531079
202. H. Yun, G. Yao, R. Pellizzoni, M. Caccamo, and L. Sha. 2016. Memory bandwidth management for efficient performance isolation in multiCore platforms. In IEEE Trans.comput. IEEE, 562-576.
203. R. Zalman, A. Griessing, and P. Emberson. 2011. Timing correctness in safetyRelated automotive software. In SAE Tech. Papers. SAE. DOI:https://doi.org/10.4271/2011-01-0449
204. M. Zimmer, D. Broman, C. Shaver, and E. A. Lee. 2014. FlexPRET: A processor platform formixedCriticality systems. In Proceedings of the IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS'14). 101-110.DOI:https://doi.org/10.1109/RTAS.2014.6925994
205. M. P. Zimmer. 2015. Predictable Processors for MixedCriticality Systems and Precision-Timed I/O. Thesis, University of California, Berkeley.