NMOS and PMOS transistors fabricated in strained silicon/relaxed silicon-germanium structures

Technical Digest - International Electron Devices Meeting, IEDM

Volumn 1992-December, Issue , 1992, Pages 1000-1002

  Welser, J ^a   Hoyt, J L ^a   Gibbons, J F ^a  

^a Solid State Electron Lab ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRON MOBILITY; ELECTRONS; FABRICATION; GERMANIUM; MOS DEVICES; MOSFET DEVICES; SEMICONDUCTOR ALLOYS; SI-GE ALLOYS; TRANSISTORS;

EPITAXIAL LAYER STRUCTURES; MOBILITY ENHANCEMENT; MODULATION-DOPED STRUCTURES; PMOS TRANSISTORS; SILICON GERMANIUM; STRAIN-INDUCED BAND SPLITTING; TEMPERATURE PERFORMANCE; THEORETICAL CALCULATIONS;

STRAINED SILICON;

EID: 85058698601     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.1992.307527     Document Type: Conference Paper

References (7)

1. T. Vogelsang and K. Hoffman, in DRC Tech. Dig., June, 1992
2. Y. J. Mii, et al., Appl. Phys. Lett, 59, p. 1611 (1991).
3. K. Ismail, et al., IEEE Elec. Dev. Lett., 13 p. 229 (1992).
4. A. G. Sabnis and J. T. Clemens, in IEDM Tech. Dig., p. 18 (1979).
5. S. C. Sun and J. D. Plummer, IEEE Trans. Elec. Dev., ED-27, p. 1497 (1980).
6. B. Majkusiak and A. Jakubowski, IEEE Trans. Elec. Dev., ED-33, p. 1717 (1986).
7. V. P. Kesan, et al., in Mat. Res. Soc. Proc. Vol. 20, p. 471 (1991).