5 V-To-75 v CMOS output interface circuits

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 1993, Pages 162-163

  Declerq, M J ^a   Schubert, M ^a   Clement, F ^a  

^a EPFL   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

TIMING CIRCUITS;

CMOS TECHNOLOGY; GATE-TO-SOURCE VOLTAGES; LOW VOLTAGE CMOS TECHNOLOGY; OUTPUT DEVICES; OUTPUT INTERFACE; OUTPUT VOLTAGE SWINGS; SAFETY LIMITS; STATIC CIRCUIT;

CMOS INTEGRATED CIRCUITS;

EID: 85057115507     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.1993.280014     Document Type: Conference Paper

References (5)

1. Parpis, Z., et sI., "Modeling and Characterizatien of CMOSCempstible High-Voltage Device Structures", IEEE Trsns. El. Devices, vol. ED-34, ne. 10, pp. 2305-2343, Nov. 1987.
2. Apel, U., et at., "High-Voltage CMOS Transistors ins Low-Voltage CMOS Process", Proceedings of the tot. Symposium on Sigosls, Systems aod Electronics, pp. 52-55, URSI, 1989.
3. Patent pendiog
4. Degreuwe, M. C., stat., "Adsptstiee Bissiog CMOS Amplifiers", jggg J. of Solid-Stale Circuits, vol. SC-i. no.3, pp. 522-528, June 1982
5. Castello, R, "CMOS Buffer Amplifiers", CMOS & BiCMOS VLSI Desigo 92, EPFL-LEG Intensive Summer Course, Aug. 17-Sept. 4, 1992.