A high speed SOI technology with 12 ps/18 ps gate delay operating at 5V/1.5V

Technical Digest - International Electron Devices Meeting, IEDM

Volumn 1992-December, Issue , 1992, Pages 35-38

  Chen, Jian ^a,b   Parke, S ^a   King, J ^a   Assaderaghi, F ^a   Ko, P K ^a   Hu, Chenming ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b ADVANCED MICRO DEVICES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FIELD EFFECT TRANSISTORS; LOW POWER ELECTRONICS;

AT POWER SUPPLIES; DEPLETION MODES; HIGH-PERFORMANCE CIRCUITS; LOW POWER SUPPLY VOLTAGE; POWER SUPPLY VOLTAGE; PROPAGATION DELAYS; RING OSCILLATOR; SOI TECHNOLOGY;

SILICON ON INSULATOR TECHNOLOGY;

EID: 85051959597     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.1992.307303     Document Type: Conference Paper

References (6)

1. J-P. Colinge, "Silicon-on-Insulator Technology: Materials to VLSI", Kluwer Academic Publishers, 1991.
2. M. Yoshimi et al, "Two-Dimensional Simulation and Measurement of High Performance MOSFET's Made on a Very Thin SOI Film", IEEE Trans on Electron Devices, vol. 36, No. 3, 1989.
3. S. Parke et al, "A Versatile, SOI BiCMOS Technology with Complementary Lateral BJT's", 1992 IEDM.
4. J. Chen et al, "The Enhancement of GIDL Current in SOI MOSFET and Its Impact on SOI Device Scaling", 1992 IEEE SOI Conference.
5. T. Elewa et al, "Detailed Analysis of Edge Effects in SIMOX-MOS Transistors", IEEE Trans on Electron Devices, vol. 39, No. 4, 1992.
6. A. Kamgar et al, "Ultra-Fast (0. 5mm) CMOS Circuits in Fully Depleted SOI Films", IEEE Trans on Electron Devices, vol. 39, No. 3, 1992.