Automatic system level test generation and fault location for large digital systems

Proceedings - Design Automation Conference

Volumn , Issue , 1978, Pages 347-352

  Yamada, A ^a   Wakatsuki, N ^a   Fukui, T ^a   Funatsu, S ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; LOCATION;

AUTOMATIC PARTITIONING; AUTOMATIC SYSTEMS; AUTOMATIC TEST GENERATION; DIGITAL SYSTEM; LOCATION TECHNIQUES; SCAN PATH; TEST GENERATIONS;

MULTIPROCESSING SYSTEMS;

EID: 85051679516     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DAC.1978.1585196     Document Type: Conference Paper

References (7)

1. J. P. Roth, W. G. Bouricius, and P. R. Scheider, "Programmed algorithms to compute tests to detect and distinguish between failures in logic circuits", IEEE TRANS, on EC, Vol. EC-16, No. 5, Oct. 1967.
2. G. R. Putzolu and J. P. Roth, "A Heuristic Algorithm for the Testing of Asynchronous Circuits", IEEE Trans, on C, Vol. C-20, No. 6, June 1971.
3. W. C. Carter, H. C. Montgomery, R. J. Preiss, and H. J. Reinheimer, "Design of serviceability features for the IBM system/360", IBM J. Res. Develop., Vol. 8, Apr. 1964.
4. B. W. Clark "Automated Fault Location on Processing Unit", Automated Support Systems Simposium for Advanced Maintenability, 1967.
5. S. Funatsu, N. Wakatsuki and T. Arima "Test Generation Systems in Japan", Proc. 12th Design Automation Conf., June 1975.
6. E. B. Eichelberger", A Logic Design Structure for LSI Testability", Proc. 14th Design Automation Conf., June, 1977.
7. P. S. Bottorff, R. E. France, N. H. Garges and E. J. Orosz, "Test Generation for Large Logic Networks", Proc. 14th Design Automation Conf., June 1977.