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Volumn , Issue , 1979, Pages 287-289

Optimal layout of CMOS functional arrays

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; GRAPH THEORY; INTEGRATED CIRCUIT LAYOUT;

EID: 85051629007     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DAC.1979.1600120     Document Type: Conference Paper
Times cited : (7)

References (11)
  • 1
    • 0004166884 scopus 로고
    • Mos/lsi design and application
    • New York, New York: McGraw-Hill Book Company
    • Carr, W. N, and J. P. Mize "MOS/LSI Design and Application, " Texas Instruments Electronics Series, New York, New York: McGraw-Hill Book Company, 1972, .
    • (1972) Texas Instruments Electronics Series
    • Carr, W.N.1    Mize, J.P.2
  • 2
    • 0014980091 scopus 로고
    • Synthesis of networks with a minimum number of negative gates
    • January
    • Ibaraki, T. and S. Muroga "Synthesis of Networks with a Minimum Number of Negative Gates, " IEEE Transaction on Computers, Vol. C-20 January 1971, pp. 49-58.
    • (1971) IEEE Transaction on Computers , vol.C-20 , pp. 49-58
    • Ibaraki, T.1    Muroga, S.2
  • 5
    • 84939058682 scopus 로고
    • Silicon-on-sapphire technology produces high-speed single-chip processor
    • April
    • Forbes, B E. "Silicon-on-Sapphire Technology Produces High-Speed Single-Chip Processor, " Hewlett- Packerd Journal, April 1977, pp. 2-8.
    • (1977) Hewlett- Packerd Journal , pp. 2-8
    • Forbes, B.E.1
  • 6
    • 0345056867 scopus 로고
    • Large scale integration of MOS complex logic: A layout method
    • December
    • Weinberger, A. "Large Scale Integration of MOS Complex Logic: A Layout Method, " IEEE Journal of Solid State Circuits, Vol. 2, December 1967, pp. 182 -190.
    • (1967) IEEE Journal of Solid State Circuits , vol.2 , pp. 182-190
    • Weinberger, A.1
  • 7
    • 84976717328 scopus 로고
    • Automatic layout of low-cost quick-Turnaround random-logic LSI devices
    • San Francisco, June
    • Feller, A. "Automatic Layout of Low-Cost Quick- Turnaround Random-Logic LSI Devices, " Proceeding of the 13th Design Automation Conference, San Francisco, June 1976, pp. 79-85.
    • (1976) Proceeding of the 13th Design Automation Conference , pp. 79-85
    • Feller, A.1
  • 9
    • 0003780715 scopus 로고
    • Reading, Massachusetts: Addison-Wesley
    • Harary, F, "Graph Theory, " Reading, Massachusetts: Addison-Wesley, 1969.
    • (1969) Graph Theory
    • Harary, F.1
  • 10
    • 85051625482 scopus 로고
    • Optimal layout of CMOS functional arrays
    • Digital Systems Laboratory, Stanford University, March
    • Uehara, T. and vanCleemput, N. M, "Optimal Layout of CMOS Functional Arrays, " Technical Report Ho.142, Digital Systems Laboratory, Stanford University, March 1975.
    • (1975) Technical Report Ho.142
    • Uehara, T.1    Van Cleemput, N.M.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.