Placement algorithms for arbitrarily shaped blocks

Proceedings - Design Automation Conference

Volumn , Issue , 1979, Pages 474-480

  Preas, B T ^a   VanCleemput, M M ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; INTEGRATED CIRCUIT INTERCONNECTS; VLSI CIRCUITS;

CIRCUIT FUNCTIONS; HIERARCHICAL DECOMPOSITIONS; HIERARCHICAL LEVEL; ITERATIVE IMPROVEMENTS; PLACEMENT ALGORITHM; RECTANGULAR BLOCK; SIZE AND SHAPE; VERY LARGE SCALE INTEGRATED;

ITERATIVE METHODS;

EID: 85050909886     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DAC.1979.1600152     Document Type: Conference Paper

References (11)

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3. Preas, B.T. and Gwyn, C.N. "Architecture for Contemporary Computer Aids to Generate IC Mask Layouts, " Conf. Record 11th Asilomar Conf. on Circuits, Systems and Computers, November 1977, PP. 353-361.
4. Preas, B.T. and Gwyn, C.M. "Methods for Hierarchical Automatic Layout of Custom LSi Circuit Masks, " Proc. 15th Desiqn Automation Conf., Las Vegas, Nevada. June 1978, pp. 206-212.
5. Preas, B.T. and vanCleemput, M.M. "Routing Algorithms for Hierarchical IC Layout, " ProD. Int. Symp. Circuits and Systems, Tokyo, Japan, 1979.
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8. Gilmore, P.C. and Oomory, R.E. "Multi-stage Cutting Stock Problems of Two and More Dimensions, " Operations Res., vol. 13, January-February 1965, pp. 94-120.
9. Kato, H., Kawanishi, H., Goto, S., Oyamada, T. and Kani, K. "On Automated Wire Routing for Building-Block HOS LSI, " proc. Int. Symp. Circuits and Systems, San Francisco, California April 1974, pp. 309-313.
10. Moder, J.J. and Phillips, C.R. Project Manaaement with CPM and PERT New York: VanNostrand, 1970.
11. Feller, A. "Automatic Layout of Low-Cost Quick- Turnaround Random-Logic Custom LSI Devices, " Proc. 13th ~ Automation Conf., San Francisco California, June 1976, pp. 79-85.