Leveraging thermally-aware chiplet organization in 2.5D systems to reclaim dark silicon

Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018

Volumn 2018-January, Issue , 2018, Pages 1441-1446

  Eris, Furkan ^a   Joshi, Ajay ^a   Kahng, Andrew B ^b,c   Ma, Yenai ^a   Mojumder, Saiful ^a   Zhang, Tiansheng ^a  

^a BOSTON UNIVERSITY   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COSTS; MANUFACTURE; SILICON;

GREEDY APPROACHES; HIGHER FREQUENCIES; MANUFACTURING COST; OPTIMAL SOLUTIONS; OPTIMIZATION PROBLEMS; PEAK TEMPERATURES; TEMPERATURE THRESHOLDS; THERMAL CONSTRAINTS;

COST BENEFIT ANALYSIS;

EID: 85048772713     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.23919/DATE.2018.8342238     Document Type: Conference Paper

References (36)

1. M. Shafique et al., "The EDA challenges in the dark silicon era:temperature, reliability, and variability perspectives, " in Proc. DAC, 2014, pp. 1-6.
2. T. Muthukaruppan et al., "Hierarchical power management for asymmetric multi-core in dark silicon era, " in Proc. DAC, 2013, pp. 1-9.
3. G. Venkatesh et al., "Qscores: Trading dark silicon for scalable energy efficiency with quasi-specific cores, " in Proc. MICRO, 2011, pp. 163-174.
4. C. Silvano et al., "Voltage island management in near threshold manycore architectures to mitigate dark silicon, " in Proc. DATE, 2014, p. 201.
5. J. Han et al., "Approximate computing: An emerging paradigm for energyefficient design, " in Proc. ETS. IEEE, 2013, pp. 1-6.
6. S. Pagani et al., "TSP: thermal safe power: efficient power budgeting for many-core systems in dark silicon, " in Proc. CODES+ISSS, 2014, p. 10.
7. A. Raghavan et al., "Computational sprinting, " in Proc. HPCA, 2012, pp. 1-12.
8. G. H. Loh, Y. Xie, and B. Black, "Processor design in 3D die-stacking technologies, " IEEE Micro, vol. 27, no. 3, 2007.
9. A. Kannan et al., "Enabling interposer-based disintegration of multi-core processors, " in Proc. MICRO, 2015, pp. 546-558.
10. D. Stow et al., "Cost analysis and cost-driven IP reuse methodology for SoC design based on 2. 5D/3D integration, " in Proc. ICCAD, 2016, p. 56.
11. "DARPA CHIPS, " http://www. darpa. mil/news-events/2016-07-19, 2016.
12. P. Grani et al., "Photonic interconnects for interposer-based 2. 5D / 3D integrated systems on a chip, " in Proc. MEMSYS, 2016, pp. 377-386.
13. J. Charbonnier et al., "High density 3D silicon interposer technology development and electrical characterization for high end applications, " in Proc. ESTC, 2012, pp. 1-7.
14. R. Chaware, K. Nagarajan, and S. Ramalingam, "Assembly and reliability challenges in 3D integration of 28nm FPGA die on a large high density 65nm passive interposer, " in Proc. ECTC, 2012, pp. 279-283.
15. W.-L. Hung et al., "Thermal-aware floorplanning using genetic algorithms, " in Proc. ISQED, 2005, pp. 634-639.
16. M. Healy et al., "Multiobjective microarchitectural floorplanning for 2D and 3D ICs, " IEEE TCAD, vol. 26, no. 1, pp. 38-52, 2007.
17. D. Cuesta et al., "Thermal-aware floorplanning exploration for 3D multicore architectures, " in Proc. GLSVLSI, 2010, pp. 99-102.
18. F. Frantz, L. Labrak, and I. O'Connor, "3D IC floorplanning: Automating optimization settings and exploring new thermal-aware management techniques, " Microelectronics Journal, vol. 43, no. 6, pp. 423-432, 2012.
19. J. Howard et al., "A 48-core IA-32 processor in 45 nm CMOS using ondie message-passing and DVFS for performance and power scaling, " IEEE JSSC, vol. 46, no. 1, pp. 173-183, 2011.
20. T. Zhang et al., "Thermal management of manycore systems with siliconphotonic networks, " in Proc. DATE, 2014, pp. 1-6.
21. Z. Zhang et al., "Recent advances in flip-chip underfill: materials, process, and reliability, " IEEE Trans. Adv. Pack., vol. 27, no. 3, pp. 515-524, 2004.
22. C. Sun et al., "DSENT-a tool connecting emerging photonics with electronics for opto-electronic networks-on-chip modeling, " in Proc. NOCS, 2012, pp. 201-210.
23. M. A. Karim, P. D. Franzon, and A. Kumar, "Power comparison of 2D, 3D and 2. 5D interconnect solutions and power optimization of interposer interconnects, " in Proc. ECTC, 2013, pp. 860-866.
24. T. E. Carlson et al., "Sniper: exploring the level of abstraction for scalable and accurate parallel multi-core simulation, " in Proc. SC, 2011, p. 52.
25. G. Parès, "3D technology for photonics silicon interposer, " in Green IT workshop-Leti Days, 2013.
26. K. Tran et al., "High-bandwidth memory white paper: Start your HBM/2. 5D design today, " Amkor Technology Inc., Tech. Rep., 2016.
27. S. Farrens, "Wafer and die bonding technologies for 3d integration, " in Proc. MRS, 2008, pp. 1112-E01.
28. R. Zhang et al., "Hotspot 6. 0: Validation, acceleration and extension, " 2015.
29. K. Ruhmer et al., "Lithography challenges for 2. 5D interposer manufacturing, " in Proc. ECTC, 2014, pp. 523-527.
30. S. C. Woo et al., "The SPLASH-2 programs: Characterization and methodological considerations, " in Proc. ISCA, 1995, pp. 24-36.
31. C. Bienia et al., "The PARSEC benchmark suite: characterization and architectural implications, " in Proc. PACT, 2008, pp. 72-81.
32. M. Heroux, "HPCCG MicroApp, " 2007.
33. D. Campbell et al., "Ubiquitous high performance computing: Challenge problems specification, " GaTech, Tech. Rep. HR0011-10-C-0145, 2012.
34. S. Li et al., "McPAT: an integrated power, area, and timing modeling framework for multicore and manycore architectures, " in Proc. MICRO, 2009, pp. 469-480.
35. J. Meng, K. Kawakami, and A. K. Coskun, "Optimizing energy efficiency of 3-D multicore systems with stacked dram under power and thermal constraints, " in Proc. DAC, 2012, pp. 648-655.
36. E. Friedman, Personal Communication, Dec. 2016.