Digital neural network implementation

11th Annual International Phoenix Conference on Computers and Communication, IPCCC 1992 - Proceedings

Volumn , Issue , 1992, Pages 722-728

  Swartzlander, E E ^a   Jones, R F ^b  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

^b ADVANCED MICRO DEVICES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COUNTING CIRCUITS; NETWORK LAYERS;

BINARY SIGNALS; PARALLEL COUNTERS; SINGLE-BIT;

MULTILAYER NEURAL NETWORKS;

EID: 85045844871     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PCCC.1992.200512     Document Type: Conference Paper

References (9)

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2. E. E. Swartzlander, Jr., "The Quasi-Serial Multiplier, " IEEE Transactions on Computers, Vol. C-22, pp. 317-321, 1973.
3. L. Dadda, "Some Schemes for Parallel Multipliers, " Alta Frequenza, Vol. 34, pp. 349-356, 1965.
4. L. Dadda, "On Parallel Digital Multipliers, " Alta Frequenza, Vol. 45, pp. 574-580, 1976.
5. I. T. Ho and T. C. Chen, "Multiple Addition by Residue Threshold Functions and Their Representation by Array Logic, " IEEE Transactions on Computers, Vol. C-22, pp. 762-767, 1973.
6. A. Svoboda, "Adder with Distributed Control, " IEEE Transactions on Computers, Vol. C-19, pp. 749-751, 1970.
7. D. Zhang, et al., "Arithmetic for Digital Neural Networks, " Proceedings of the 10th Symposium on Computer Arithmetic, pp. 58-63, 1991.
8. E. E. Swartzlander, Jr., B. K. Gilbert, I. S. Reed, "Inner Product Computers, " IEEE Transactions on Computers, Vol. C-27, pp. 21-31, 1978.
9. E. E. Swartzlander, Jr., "Wafer Scale Integration for the Implementation of Artificial Neural Networks, " in M. Sami and J. Calzadilla-Daguerre, eds., Silicon Architectures for Neural Nets, New York: North-Holland, 1991, pp. 179-185.