Mapping homogeneous computations onto dynamically configurable coarse-grained architectures

Proceedings - IEEE Symposium on FPGAs for Custom Computing Machines, FCCM 1998

Volumn 1998-April, Issue , 1998, Pages 314-315

  Dandalis, A ^a   Prasanna, V K ^a  

^a University of Southern California   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATION THEORY; COMPUTERS; EFFICIENCY; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); MAPPING; MEMORY ARCHITECTURE;

COMPUTING-TASK; CONFIGURABLE ARCHITECTURES; DYNAMIC COMPUTATIONS; DYNAMIC STRUCTURE; HIGH THROUGHPUT; ORIENTED STRUCTURE; PROCESSING ELEMENTS; RESEARCH GROUPS;

COMPUTATIONAL EFFICIENCY;

EID: 85041538638     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPGA.1998.707933     Document Type: Conference Paper

References (3)

1. A. Dandalis and V. K. Prasanna, "Fast Parallel Implementation of DFT using Configurable Devices", Int. Workshop on Field Programmable Logic and Applications, Sep. 1997.
2. C. Ebeling, D. C. Cronquist, P. Franklin and C. Fisher, "RaPiD - A configurable computing architecture for compute-intensive applications", Technical Report UW- CSE-96-11-03, Nov. 1996.
3. A. Dandalis and V. K. Prasanna, "Mapping Heterogeneous Computations onto Dynamically Configurable Coarse-Grained Architectures", Manuscript, Jan. 1998.