CMOS Scaling Trends and beyond

IEEE Micro

Volumn 37, Issue 6, 2017, Pages 20-29

  Bohr, Mark T ^a   Young, Ian A ^b  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Beyond CMOS; CMOS scaling; logic transistors; Moore's law

Indexed keywords

HARDWARE; MICROWAVE INTEGRATED CIRCUITS;

BEYOND CMOS; CMOS SCALING; COST IMPROVEMENTS; MOORE'S LAW; NEW DEVICES;

CMOS INTEGRATED CIRCUITS;

EID: 85038127830     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2017.4241347     Document Type: Article

References (16)

1. G. Moore, "Cramming More Components onto Integrated Circuits," Electronics, vol. 38, no. 8, 1965, pp. 114-117.
2. G. Moore, "Progress in Digital Integrated Electronics," IEEE Int'l Electron Devices Meeting Technical Digest, 1975, pp. 11-13.
3. R. Dennard et al., "Design of Ion-Implanted MOSFETs with Very Small Physical Dimensions," IEEE J. Solid State Circuits, vol. 9, no. 5, 1974, pp. 256-268.
4. T. Ghani et al., "A 90nm High Volume Manufacturing Logic Technology Featuring Novel 45nm Gate Length Strained Silicon CMOS Transistors," IEEE Int'l Electron Devices Meeting Technical Digest, 2003, pp. 978-980.
5. K. Mistry et al., "A 45nm Logic Technology with High-k 1 Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging," IEEE Int'l Electron Devices Meeting Technical Digest, 2007, pp. 247-250.
6. A.C. Auth et al., "A 22nm High Performance and Low-Power CMOS Technology Featuring Fully-Depleted Tri-gate Transistors, Self-Aligned Contacts and High Density MIM Capacitors," Proc. Symp. VLSI Technology, 2012, pp. 131-132.
7. S. Natarajan et al., "A 14nm Logic Technology Featuring 2nd Generation FinFET Transistors, Air-Gapped Interconnects, Self-Aligned Double Patterning and a 0.0588um2 SRAM Cell Size," IEEE Int'l Electron Devices Meeting Technical Digest, 2014, pp. 71-74.
8. R. Kim, U.E. Avci, and I.A. Young, "Comprehensive Performance Benchmarking of III-V and Si nMOSFETs (Gate Length 5 13 nm) Considering Supply Voltage and OFF-Current," IEEE Trans. Electron Devices, vol. 62, no. 3, 2015, pp. 713-721.
9. U.E. Avci et al., "Energy Efficiency Comparison of Nanowire Heterojunction TFET and Si MOSFET at Lg 5 13 nm, Including P-TFET and Variation Considerations," IEEE Int'l Electron Devices Meeting Technical Digest, 2013, pp. 33-36.
10. W.M. Holt, "1.1 Moore's Law: A Path Going Forward," Proc. IEEE Int'l Solid-State Circuits Conf., 2016, pp. 8-13.
11. J.J. Welser et al., "The Quest for the Next Information Processing Technology," J. Nanoparticle Research, vol. 10, 2008, pp. 1-10.
12. D.E. Nikonov and I.A. Young, "Overview of Beyond-CMOS Devices and a Uniform Methodology for their Benchmarking," Proc. IEEE, vol. 101, no. 12, 2013, pp. 2498-2533.
13. D.E. Nikonov and I.A. Young, "Benchmarking of Beyond-CMOS Exploratory Devices for Logic Integrated Circuits," IEEE J. Exploratory Solid-State Computational Devices and Circuits, vol. 1, 2015, pp. 3-11.
14. I.P. Radu et al., "Spintronic Majority Gates," IEEE Int'l Electron Devices Meeting Technical Digest, 2015, p. 32.5.1-32.5.4.
15. S. Borkar, "Electronics Beyond Nano-Scale CMOS," Proc. 43rd ACM/IEEE Design Automation Conf., 2006, pp. 807-808.
16. I.A. Young and D.E. Nikonov, "Principals and Trends in Quantum Nano-Electronics and Nano-Magnetics for Beyond CMOS Computing," to be published in Proc. European Solid-State Device Research Conf., 2017.