Design of an MPEG-2 codec

IEEE Signal Processing Magazine

Volumn 19, Issue 4, 2002, Pages 32-41

  Konstantinides, Konstantinos ^a,b   Chen, Cheng Tie ^a   Chen, Ting Chung ^a   Cheng, Hown ^a   Jeng, Fure Ching ^a  

^a Cirrus Logic   (United States)

^b IEEE   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BANDWIDTH; CMOS INTEGRATED CIRCUITS; COMPUTER SOFTWARE; COSINE TRANSFORMS; DATA TRANSFER; DECODING; DIGITAL INTEGRATED CIRCUITS; DIGITAL SIGNAL PROCESSING; IMAGE CODING; IMAGE COMPRESSION; MOTION ESTIMATION; REDUCED INSTRUCTION SET COMPUTING; SHIFT REGISTERS; STATIC RANDOM ACCESS STORAGE;

VIDEO INPUT UNITS (VIU);

INTEGRATED CIRCUIT LAYOUT;

EID: 85032751890     PISSN: 10535888     EISSN: None     Source Type: Journal    
DOI: 10.1109/MSP.2002.1012348     Document Type: Article

References (21)

1. A single-chip MPEG-2 video encoder/decoder for consumer applications
2. Design of a personal digital video recorder/player
3. A single-chip MPEG-2 MP@ML audio/video encoder/decoder with a programmable video interface unit
4. Two-pass MPEG-2 variable-bit-rare encoding
5. Single-pass constant-and variable-bit-rate MPEG-2 video compression