Reconciling Time Predictability and Performance in Future Computing Systems

IEEE Design and Test

Volumn 35, Issue 2, 2018, Pages 48-56

  Cazorla, Francisco J ^a   Abella, Jaume ^a   Mezzetti, Enrico ^a   Hernandez, Carles ^a   Vardanega, Tullio ^b   Bernat, Guillem ^c  

^a BARCELONA SUPERCOMPUTING CENTER   (Spain)

^b UNIVERSITY OF PADOVA   (Italy)

^c RAPITA SYSTEMS LTD   (United Kingdom)

Author keywords

C.0.d Modeling of computer architecture; C.3.d Real time and embedded systems

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER HARDWARE; COMPUTER SOFTWARE; COST EFFECTIVENESS; EMBEDDED SYSTEMS; HARDWARE; INTERACTIVE COMPUTER SYSTEMS; MONITORING; PHASOR MEASUREMENT UNITS; UNITS OF MEASUREMENT;

HIGH-PERFORMANCE HARDWARE; ORDERS OF MAGNITUDE; PERFORMANCE EVALUATION; PERFORMANCE GUARANTEES; REAL-TIME AND EMBEDDED SYSTEMS; TIME PREDICTABILITIES; TIMING; TIMING VERIFICATION;

REAL TIME SYSTEMS;

EID: 85032448566     PISSN: 21682356     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDAT.2017.2766558     Document Type: Article

References (12)

1. High-Performance Embedded Architecture and Compilation. HiPEAC vision. 2011, 2013, 2015, and 2017.
2. P. K. Valsan, H. Yun, and F. Farshchi, "Taming nonblocking caches to improve isolation in multicore real-time systems," in Proc. 2016 IEEE Real-Time Embed. Tech. Appl. Symp. (RTAS), Vienna, Austria, Apr. 2016, pp. 1-12.
3. Precision Timed Machines. [Online]. Available: Http://chess.eecs.berkeley.edu/pret
4. Time-Predictable Multicore Architecture for Embedded Systems. [Online]. Available: Http://www.t-crest.org/
5. M. Panic, C. Hernandez, J. Abella, A. Roca, E. Quinones, and F. J. Cazorla, "Improving performance guarantees in wormhole mesh NOC designs." in Proc. 2016 Des., Automat. Test in Europe Conf. Exhibit. (DATE 2016), Dresden, Germany, Mar. 2016, pp. 1485-1488.
6. G. Fernandez, J. Jalle, J. Abella, E. Quinones, T. Vardanega, and F. J. Cazorla, "Increasing confidence on measurement-based contention bounds for real-time round-robin buses" in Proc. 52nd Ann. Des. Automat. Conf. (DAC '15), New York, NY, USA, 2015, pp. 125:1-125:6.
7. J. Jalle, J. Abella, E. Quinones, L. Fossati, M. Zulianello, and F. J. Cazorla, "AHRB: A high-performance time-composable AMBA AHB bus," in Proc. 20th IEEE Real-Time Embed. Tech. Appl. Symp. (RTAS 2014), Berlin, Germany, Apr. 2014.
8. R. Wilhelm et al., "The worst-case execution-time problem: Overview of methods and survey of tools." ACM Transact. Embed. Comput. Sys., pp. 7:1-7:53, May 2008.
9. L. Kosmidis et al., Fitting processor architectures for measurement-based probabilistic timing analysis. Microprocessors and Microsystems, vol. 47, no. PB, pp. 287-302, 2016.
10. C. Hernandez, J. Abella, A. Gianarro, J. Andersson, and F. J. Cazorla, "Random modulo: A new processor cache design for real-time critical systems," in Proc. 2016 53rd ACM/EDAC/IEEE Des. Automat. Conf. (DAC), Jun. 2016, pp. 1-6.
11. J. Abella, M. Padilla, J. Del Castillo, and F. J. Cazorla, "Measurement-based worst-case execution time estimation using the coefficient of variation," ACM Trans. Des. Autom. Electron. Syst., vol. 22, no. 4, pp. 72:1-72:29, 2017.
12. N. R. Adiga et al., "Blue gene/l torus interconnection network," IBM J. Res. Dev., vol. 49, no. 2.3, pp. 265-276, 2005.