Design for testability of gated-clock FSMs

Proceedings of the 1996 European Conference on Design and Test, EDTC 1996

Volumn , Issue , 1996, Pages 589-596

  Favalli, M ^a   Benini, L ^b   De Micheli, G ^b  

^a UNIVERSITY OF BOLOGNA   (Italy)

^b STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN FOR TESTABILITY; OBSERVABILITY; REDUNDANCY;

DESIGN PRACTICE; GATED CLOCKS; POWER SAVINGS; REDUNDANCY REMOVAL; SYNCHRONOUS SYSTEM; TESTABILITY; FINITE-STATE;

CLOCKS;

EID: 85030124698     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EDTC.1996.494361     Document Type: Conference Paper

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