A 0.72 μm2 recessed STC (RSTC) technology for 256 Mbit DRAMs using quarter-micron phase-shift lithography

Digest of Technical Papers - Symposium on VLSI Technology

Volumn 1992-June, Issue , 1992, Pages 10-11

  Sagara, K ^a   Kure, T ^a   Shukuri, S ^a   Yugami, J ^a   Hascgawa, N ^a   Shinriki, H ^a   Goto, H ^a   Yamashit, H ^a   Takcda, E ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; DYNAMIC RANDOM ACCESS STORAGE;

CELL CAPACITANCE; FINE PATTERN; MEMORY ARRAY; PHASE SHIFT LITHOGRAPHY; PLATE TECHNOLOGIES;

VLSI CIRCUITS;

EID: 85029999454     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.1992.200618     Document Type: Conference Paper

References (4)

1. H.Watanabc et al., "An advanced Fabrication of Hemispherical Grained (HSG) Poly-Si for High Capacitance Storage Electrodes, " Extended Abstracts of the 1991 International Conferenece on SSoM, pp.478-480, August 1991.
2. H.Fukuda and S.Okazaki, "Super-Resolution Optical Lithography, " Kougaku (in Japancscs), vol.19, pp.290-294, May 1990.
3. M.D.Levenson, N.S.Visnawathan and R.A.Simpson, "Improving Resolution in Photolithography with a Phasc-sliifling Mask, " IEEE Transactions on Electron Devices, vol.ED-29, pp. 1828-1836, December 1982.
4. H.Goto, N.Kobayashi and Y.Hotnma, "Conformal and Low Temperature W-CVD by SiJLR Reduction, " Extended Abstracts of the International Conference on SSDM, pp.183-185, August 1991.