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Volumn 697 LNCS, Issue , 1993, Pages 41-58

BDD-based debugging of designs using language containment and fair CTL

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATA THEORY; BINARY DECISION DIAGRAMS; BOOLEAN FUNCTIONS; COMPUTER AIDED ANALYSIS; MODEL CHECKING;

EID: 85029447723     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-56922-7_5     Document Type: Conference Paper
Times cited : (28)

References (13)
  • 4
    • 0022706656 scopus 로고
    • Automatic Verification of Finite-State Concurrent Systems Using Temporal Logic Specifications
    • E. M. Clarke, E. A. Emerson, A. P. Sistla. “Automatic Verification of Finite-State Concurrent Systems Using Temporal Logic Specifications”, ACM Transactions on Programming Languages and Systems. 8(2):244-263, 1986.
    • (1986) ACM Transactions on Programming Languages and Systems , vol.8 , Issue.2 , pp. 244-263
    • Clarke, E.M.1    Emerson, E.A.2    Sistla, A.P.3
  • 5
    • 0023362541 scopus 로고
    • Modalities for Model Checking: Branching Time Logic Strikes Back
    • Elsevier Science Publishers
    • E. A. Emerson, C. L. Lei, “Modalities for Model Checking: Branching Time Logic Strikes Back”, Science of Computer Programming 8, 275-306, Elsevier Science Publishers, 1987.
    • (1987) Science of Computer Programming , vol.8 , pp. 275-306
    • Emerson, E.A.1    Lei, C.L.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.