Minimalist design for accelerating convolutional neural networks for low-end FPGA platforms

Proceedings - IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2017

Volumn , Issue , 2017, Pages 196-

  Morcel, Raghid ^a   Akkary, Haitham ^a   Hajj, Hazem ^a   Saghir, Mazen ^a   Keshavamurthy, Anil ^b   Khanna, Rahul ^b   Artail, Hassan ^a  

^a AMERICAN UNIVERSITY OF BEIRUT   (Lebanon)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTERS; DEEP LEARNING; DEEP NEURAL NETWORKS; DESIGN; EDUCATION; INTEGRATED CIRCUIT DESIGN; INTERNET OF THINGS; LEARNING ALGORITHMS; NEURAL NETWORKS;

COMPUTATIONAL REQUIREMENTS; CONVOLUTIONAL NEURAL NETWORK; DESIGN METHODOLOGY; INDUSTRIAL COMMUNITIES; MODEL LEARNING; NEURAL NETWORK APPLICATION; RECOGNITION MODELS; STATE OF THE ART;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 85027717131     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FCCM.2017.62     Document Type: Conference Paper

References (1)

1. G. A. Krizhevsky, I. Sutskever, and G. Hinton. "Imagenet classification with deep convolutional neural networks." In Advances in neural