Analysis and implementation of packet preemption for Time Sensitive Networks

IEEE International Conference on High Performance Switching and Routing, HPSR

Volumn 2017-June, Issue , 2017, Pages

  Zhou, Zifan ^a   Yan, Ying ^a   Ruepp, Sarah ^a   Berger, Michael ^a  

^a TECHNICAL UNIVERSITY OF DENMARK   (Denmark)

Author keywords

FPGA; packet preemption; preemptive queuing; Riverbed modeler; time sensitive network (TSN); VHDL

Indexed keywords

COMPUTER HARDWARE DESCRIPTION LANGUAGES; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HARDWARE; PACKET NETWORKS; QUEUEING NETWORKS;

CRITICAL TRAFFIC; HARDWARE IMPLEMENTATIONS; PACKET PREEMPTION; PREEMPTIVE QUEUING; PRIORITY QUEUING; RIVERBED MODELER; SYSTEM LEVEL SIMULATION; TIME-SENSITIVE NETWORK (TSN);

QUEUEING THEORY;

EID: 85027244320     PISSN: 23255595     EISSN: 23255609     Source Type: Conference Proceeding    
DOI: 10.1109/HPSR.2017.7968677     Document Type: Conference Paper

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