Transistor placement and interconnect algorithms for leaf cell synthesis

Proceedings of the European Design Automation Conference, EDAC 1990

Volumn , Issue , 1990, Pages 119-123

  Lefebvre, Martin ^a   Chan, Chong ^a   Martin, Grant ^b  

^a CARLETON UNIVERSITY   (Canada)

^b NORTEL NETWORKS   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN;

GATE LEVELS; LAYOUT MASK; LEAF CELLS; PLACEMENT ALGORITHM; PLACEMENT AND ROUTING; ROUTING AREA; TRANSISTOR SIZE;

TRANSISTORS;

EID: 85027178341     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EDAC.1990.136631     Document Type: Conference Paper

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