A multi-cycle operational signal processing core for an adaptive equalizer for magnetic system application

Proceedings of IEEE Workshop on VLSI Signal Processing VI, VLSISP 1993

Volumn , Issue , 1993, Pages 150-157

  Kojima, H ^a   Tanaka, S ^a   Okada, Y ^a   Hikage, T ^a   Nakazawa, F ^a   Matsushige, H ^a   Miyasaka, H ^a   Hanamura, S ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

EQUALIZERS; FIR FILTERS; IIR FILTERS; MAXIMUM LIKELIHOOD; VLSI CIRCUITS;

ADAPTIVE EQUALIZER; CLOCK RECOVERY; DIGITAL EQUALIZERS; MAGNETIC SYSTEM; MAXIMUM LIKELIHOOD DETECTION; NUMBER OF GATES; PROPOSED ARCHITECTURES; SAMPLING PERIOD;

SIGNAL PROCESSING;

EID: 85027154147     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSISP.1993.404492     Document Type: Conference Paper

References (4)

1. T. Takashi, et al., "Digital Timing Recovery Circuit with Feedback Delay Compensators for Magnetic Recording Systems, " 1993 Symposium on VLSI Circuits, pp.77-78, 1993.
2. T. J. Schmerbeck, el al., "A 27MHz Mixed Analog/Digital Magnetic Recording Channel DSP Using Partial Response Signalling with Maximum Likelihood Detection, " IEEE ISSCC "91 TP8.3, 1993.
3. S.Tanaka, et al., "An Adaptive Equalizing, Maximum Likelihood Decoding LSI for Magnetic Recording Systems, " IEEE ISSCC'93 FA13.5, 1993.
4. T. Baji, et al., "A 20ns CMOS Micro-DSP Core for Video Signal Processing, " IEEE ISSCC '88, pp.156-157, 1988.