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Volumn , Issue , 1986, Pages 474-480

Using bottom-up design techniques in the synthesis of digital hardware from abstract behavioral descriptions

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN;

EID: 85027151577     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DAC.1986.1586131     Document Type: Conference Paper
Times cited : (58)

References (25)
  • 1
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    • J. R. Duley and D. L. Dietmeyer, "Translation of a DDL digital system specification to Boolean equations, " IEEE Transactions on Computers CIS pp. 305-313 (1969).
    • (1969) IEEE Transactions on Computers CIS , pp. 305-313
    • Duley, J.R.1    Dietmeyer, D.L.2
  • 2
    • 0004263265 scopus 로고
    • Addison-Wesley Publishing Company, Reading, Massachusetts
    • C. Mead and L. Conway, Introduction to VLSI systems, Addison-Wesley Publishing Company, Reading, Massachusetts (1980).
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    • Mead, C.1    Conway, L.2
  • 4
    • 85051641931 scopus 로고
    • A technology-relative computer-aided design system: Abstract representations, transformations, and design tradeoffs
    • ACM and IEEE
    • E. A. Snow, D. P. Siewiorek, and D. E. Thomas, "A Technology-Relative Computer-Aided Design System: Abstract Representations, Transformations, and Design Tradeoffs, " Proceedings of the 15th Design Automation Conference, pp. 220-226 ACM and IEEE, (1978).
    • (1978) Proceedings of the 15th Design Automation Conference , pp. 220-226
    • Snow, E.A.1    Siewiorek, D.P.2    Thomas, D.E.3
  • 6
    • 85051622323 scopus 로고
    • Register-transfer level digital design automation: The allocation process
    • ACM and IEEE, (June
    • L. J. Hafer and A. C. Parker, "Register-Transfer Level Digital Design Automation: The Allocation Process, " Proceedings of the 15th Design Automation Conference, pp. 213-219 ACM and IEEE, (June, 1978).
    • (1978) Proceedings of the 15th Design Automation Conference , pp. 213-219
    • Hafer, L.J.1    Parker, A.C.2
  • 8
    • 0019061388 scopus 로고
    • MDS-the mimola design method
    • G. Zimmernamm, "MDS-The Mimola Design Method, " Journal of Digital Systems 4(3) pp. 337-369 (1980).
    • (1980) Journal of Digital Systems , vol.4 , Issue.3 , pp. 337-369
    • Zimmernamm, G.1
  • 10
    • 0020989416 scopus 로고
    • MacPitts: An approach to silicon compilation
    • December
    • J. R. Southard, "MacPitts: An Approach to Silicon Compilation, " Computer 16(12) pp. 74-82 (December, 1983).
    • (1983) Computer , vol.16 , Issue.12 , pp. 74-82
    • Southard, J.R.1
  • 13
    • 0022105624 scopus 로고
    • The VLSI design automation assistant: From algorithms to silicon
    • August
    • T. J. Kowalski, D. J. Geiger, W. H. Wolf, and W. Fichtner, "The VLSI Design Automation Assistant: From Algorithms To Silicon, " Design and Test of Computers 2(4) pp. 33-43 (August, 1985).
    • (1985) Design and Test of Computers , vol.2 , Issue.4 , pp. 33-43
    • Kowalski, T.J.1    Geiger, D.J.2    Wolf, W.H.3    Fichtner, W.4
  • 16
    • 0021377635 scopus 로고
    • The VLSI design automation assistant: An IBM system/370 design
    • February
    • T. J. Kowalski and D. E. Thomas, "The VLSI Design Automation Assistant: An IBM System/370 Design, " Design and Test of Computers 1(1) pp. 60-69 (February, 1984).
    • (1984) Design and Test of Computers , vol.1 , Issue.1 , pp. 60-69
    • Kowalski, T.J.1    Thomas, D.E.2
  • 19
    • 0014129195 scopus 로고
    • Hierarchical clustering schemes
    • September
    • S. C. Johnson, "Hierarchical Clustering Schemes, " Psychome-trika 32(3) pp. 241-254 (September, 1967).
    • (1967) Psychome-trika , vol.32 , Issue.3 , pp. 241-254
    • Johnson, S.C.1
  • 20
    • 0019595341 scopus 로고
    • Some experiments in local microcode compaction for horizontal machines
    • July
    • S. Davidson, D. Landskov, B. D. Shriver, and P. W. Mallett, "Some experiments in local microcode compaction for horizontal machines, " IEEE Transactions on Computers C-30(7) pp. 460-477 (July, 1981).
    • (1981) IEEE Transactions on Computers , vol.C-30 , Issue.7 , pp. 460-477
    • Davidson, S.1    Landskov, D.2    Shriver, B.D.3    Mallett, P.W.4
  • 21
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    • A procedure for placement of standard-cell VLSI circuits
    • January
    • A. E. Dunlop and B. W. Kernighan, "A Procedure for Placement of Standard-Cell VLSI Circuits, " IEEE Transaction∗ on Computer-Aided Design CAD-4(1) pp. 92-98 (January, 1985).
    • (1985) IEEE Transaction∗ on Computer-Aided Design , vol.CAD-4 , Issue.1 , pp. 92-98
    • Dunlop, A.E.1    Kernighan, B.W.2
  • 23
    • 84990479742 scopus 로고
    • An efficient heuristic procedure for partitioning graphs
    • B. W. Kernighan and S. Lin, "An Efficient Heuristic Procedure for Partitioning Graphs, " Bell Systems Technical Journal 49 (1982).
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    • Kernighan, B.W.1    Lin, S.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.