Neuron-MOS binary-logic circuits featuring dramatic reduction in transistor count and interconnections

Technical Digest - International Electron Devices Meeting, IEDM

Volumn 1992-December, Issue , 1992, Pages 431-434

  Kotani, K ^a   Shibata, T ^a   Ohmi, T ^a  

^a TOHOKU UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRON DEVICES; INTEGRATED CIRCUIT INTERCONNECTS; LOGIC CIRCUITS; LOGIC DESIGN; TIMING CIRCUITS;

CIRCUIT CONFIGURATIONS; CMOS PROCESSS; DESIGN TECHNIQUE; FUNCTIONAL DEVICES; NEURON MOS TRANSISTORS; OPERATIONAL PRINCIPLES; TEST CIRCUIT; TRANSISTOR COUNT;

COMPUTER CIRCUITS;

EID: 85027140009     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.1992.307394     Document Type: Conference Paper

References (4)

1. T. Shibata and T. Ohmi, DIDM Tech. Dig., 1991, p. 919(1991).
2. T. Shibata and T. Ohmi, IEEE Trans. ED., ED-39, p. 1444(1992).
3. W. S. McCulloch and W. Pitts, Bull. Math. Biophys., vol. 5, p. l15, 1943.
4. T. Shibata and T. Ohmi, Dig. Tech. Papers, 1992 Symp. on VLSI Tech., p. 84(1992).