Virtual wires: Overcoming pin limitations in FPGA-based logic emulators

IEEE Symposium on FPGAs for Custom Computing Machines, Proceedings

Volumn , Issue , 1993, Pages 142-151

  Babb, J ^a   Tessier, R ^a   Agarwal, A ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; COMPUTATION THEORY; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); TOPOLOGY; WIRE;

CACHE CONTROLLER; CLOCKING FREQUENCY; COMMUNICATION BANDWIDTH; GLOBAL INTERCONNECTS; HARDWARE SUPPORTS; INTER-CHIP; NEAREST NEIGHBORS;

COMPUTER CIRCUITS;

EID: 85027124029     PISSN: 10823409     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPGA.1993.279469     Document Type: Conference Paper

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