An 8G connections-per-second 54mW digital neural network chip low-power chain-reaction architecture

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 1992-February, Issue , 1992, Pages 134-135

  Uchimura, Kuniharu ^a   Saito, Osamu ^a   Amemiya, Yoshihito ^a  

^a NTT CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

NETWORK ARCHITECTURE; NEURAL NETWORKS;

CHAIN REACTION; CMOS TECHNOLOGY; COMPUTATIONAL SPEED; FORWARD PROPAGATION; HIGH SPEED; LOW POWER;

LOW POWER ELECTRONICS;

EID: 85027123589     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.1992.200448     Document Type: Conference Paper

References (2)

1. Broomhead, D. S. and D. Lowe, "Radial Basis Functions, Multi-variable Functional Interpolation and Adaptive Networks," RSRE Memorandum No. 4148, 1988.
2. Scofield, C. L., et al., "Pattern Class Degeneracy in an Understricted Storage Density Memory," Proc. NIPS '87, p. 674 AIP, NY., 1989.