Coverage of delay faults: When 13% and 99% mean the same

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 852 LNCS, Issue , 1994, Pages 178-195

  Kraśniewski, Andrzej ^a   Wroński, Leszek B ^a  

^a WARSAW UNIVERSITY OF TECHNOLOGY   (Poland)

Author keywords

[No Author keywords available]

Indexed keywords

GRADING;

BENCHMARK CIRCUIT; CIRCUIT DELAYS; DELAY FAULT TEST; DELAY FAULT TESTABILITY; FAULT COVERAGES; GATE DELAY FAULTS; INPUT PATTERNS; TEST SEQUENCE;

DELAY CIRCUITS;

EID: 85027076730     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-58426-9_131     Document Type: Conference Paper

References (17)

1. S. Devadas, K. Keutzer, “Synthesis of Robust Delay-Fault-Testable Circuits: Theory,” IEEE Trans. Computer-Aided Design, vol. 11, pp. 87-101, Jan. 1992.
2. K. Fuchs, H. C. Wittmann, K. J. Antreich, “Fast Test Pattern Generation for All Path Delay Faults Considering Various Test Classes,” Proc. European Test Conf., pp. 89-98, 1993.
3. C. T. Glover, M. R. Mercer, “A Method of Delay Fault Test Generation,” Proc. 25th Design Automation Conf., pp. 90-95, 1988.
4. V. S. Iyengar, B. K. Rosen, J. A. Waicukauski, “On Computing the Sizes of Detected Delay Faults,” IEEE Trans. Computer-Aided Design, vol. 9, pp. 299-312, March 1990.
5. B. Könemann et al., “Delay Test: The Next Frontier for LSSD Test Systems,” Proc. Int. Test Conf., pp. 578-587, 1992.
6. A. Kraśniewski, L. B. Wroński, “Testability of Delay Faults,” Tech. Report, Warsaw Univ. of Technology, Institute of Telecommunications, Jan. 1994.
7. C. J. Lin, S. M. Reddy, “On Delay Fault Testing in Logic Circuits,” IEEE Trans. Computer-Aided Design, vol. 6, pp. 694-703, Sept. 1987.
8. W. Mat, M. D. Ciletti, “A Quantitative Measure for Robustness for Delay Fault Testing,” Proc. European Design Automation Conf., pp. 543-549, 1992.
9. P. C. Maxwell, “Let’s Grade ALL the Faults,” Proc. Int. Test Conf., pp. 595, 1993.
10. E. S. Park, M. R. Mercer, “Robust and Nonrobust Tests for Path Delay Faults in a Combinational Circuit,” Proc. Int. Test Conf., pp. 1027-1034, 1987.
11. E. S. Park, M. R. Mercer, “An Efficient Delay Test Generation System for Combinational Logic Circuits,” IEEE Trans. Computer-Aided Design, vol. 11, pp. 926-938, July 1992.
12. A.K. Prmnanick, S. M. Reddy, “On the Detection of Delay Faults,” Proc. Int. Test Conf., pp. 845-856, 1988.
13. A. K. Pramanick, S. M. Reddy, “On the Design of Path Delay Fault Testable Combinational Circuits,” Proc. 20th Fault Tolerant Computing Symp., pp. 374-381, 1990.
14. E. S. Park, B. Underwood, T. W. Williams, M. R. Mercer, “Delay Testing in Timing-Optimized Designs,” Proc. Int. Test Conf., pp. 897-905, 1991.
15. J. Savir, W. H. McAnney, “Random Pattern Testability of Delay Faults,” IEEE Trans. Computers, vol. 37, pp. 291-300, March 1988.
16. K. D. Wagner, C. K. Chin, E. J. McCluskey, “Pseudorandom Testing”, IEEE Trans. on Computers, vol. 36, pp. 332-343, Mar, 1987.
17. J. A. Waicukauski, E. Lindbloom, B. K. Rosen, V. S. Iyengar, “Transition Fault Simulation,” IEEE Design & Test of Computers, pp. 32-38, April 1987.