Formal timing analysis of non-scheduled traffic in automotive scheduled TSN networks

Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017

Volumn , Issue , 2017, Pages 1643-1646

  Smirnov, Fedor ^a   Glaß, Michael ^b   Reimann, Felix ^c   Teich, Jürgen ^a  

^a UNIVERSITY OF ERLANGEN NUREMBERG   (Germany)

^b UNIVERSITY OF ULM   (Germany)

^c AUDI ELECTRONICS VENTURE GMBH   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATION TIME; MIXED CRITICALITIES; ORDERS OF MAGNITUDE; PREPROCESSING TECHNIQUES; SCHEDULED TRAFFICS; STANDARD TIME; STATE OF THE ART; TIMING ANALYSIS;

TIMING CIRCUITS;

EID: 85020205886     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.23919/DATE.2017.7927256     Document Type: Conference Paper

References (8)

1. J. Diemer, J. Rox, et al. Modeling of Ethernet AVB networks for worstcase timing analysis. MATHMOD, 2012.
2. F. Reimann, S. Graf, et al. Timing analysis of Ethernet AVB-based automotive E/E architectures. In Proceedings of the Emerging Technologies & Factory Automation (ETFA), pp. 1-8. 2013.
3. Time Sensitive Networking Task Group of IEEE 802.1. IEEE P802.1Qbu/D3.0 Draft Standard for Local and Metropolitan Area Networks Bridges and Bridged Networks Amendment: Frame Preemption. 2015.
4. IEEE P802.1Qbv/D3.1 Draft Standard for Local and Metropolitan Area Networks Bridges and Bridged Networks Amendment: Enhancements for Scheduled Traffic. 2015.
5. K. Richter. Compositional Scheduling Analysis Using Standard Event Models. Dissertation, University of Braunschweig, 2005.
6. S. Thangamuthu, N. Concer, et al. Analysis of ethernet-switch traffic shapers for in-vehicle networking applications. In Proceedings of the Design, Automation & Test in Europe (DATE), pp. 55-60. 2015.
7. D. Thiele, R. Ernst, et al. Formal worst-case timing analysis of ethernet TSN's time-aware and peristaltic shapers. In Proceedings of the Vehicular Networking Conference (VNC), pp. 251-258. 2015.
8. L. Thiele, S. Chakraborty, et al. Real-time calculus for scheduling hard real-time systems. In Proceedings of the International Symposium on Circuits and Systems (ISCAS), pp. 101-104. 2000.