A RISC-V Processor SoC with Integrated Power Management at Submicrosecond Timescales in 28 nm FD-SOI

IEEE Journal of Solid-State Circuits

Volumn 52, Issue 7, 2017, Pages 1863-1875

  Keller, Ben ^a   Cochet, Martin ^a,b,c   Zimmer, Brian ^a,d   Kwak, Jaehwa ^a   Puggelli, Alberto ^a,e   Lee, Yunsup ^a,f   Blagojević, Milovan ^a,b,g   Bailey, Stevo ^a   Chiu, Pi Feng ^a   Dabbelt, Palmer ^a   Schmidt, Colin ^a   Alon, Elad ^a   Asanović, Krste ^a   Nikolić, Borivoje ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b STMICROELECTRONICS   (France)

^c AIX MARSEILLE UNIVERSITY   (France)

^d NVIDIA   (United States)

^e Lion Semiconductor Inc   (United States)

^f SiFive Inc   (United States)

^g INTEL DEUTSCHLAND GMBH   (Germany)

Author keywords

Adaptive clock; energy efficient processor; fine grained adaptive voltage scaling (AVS); integrated voltage regulator; power management unit (PMU); RISC V; voltage dithering

Indexed keywords

BENCHMARKING; CLOCKS; DC-DC CONVERTERS; ELECTRIC INVERTERS; ENERGY EFFICIENCY; ENERGY MANAGEMENT; ENERGY UTILIZATION; PROGRAMMABLE LOGIC CONTROLLERS; SILICON ON INSULATOR TECHNOLOGY; SYSTEM-ON-CHIP; VOLTAGE REGULATORS; VOLTAGE SCALING;

ADAPTIVE VOLTAGE SCALING; CONTINUOUS VOLTAGES; FULLY DEPLETED SILICON-ON-INSULATOR; INTEGRATED POWER MANAGEMENT; PERFORMANCE PENALTIES; POWER MANAGEMENT ALGORITHMS; SWITCHED-CAPACITOR DC-DC CONVERTER; SYSTEM ON CHIPS (SOC);

POWER MANAGEMENT;

EID: 85019025102     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2017.2690859     Document Type: Article

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