Sparse matrix-vector multiplication on multicore and accelerators

Scientific Computing with Multicore and Accelerators

Volumn , Issue , 2010, Pages 83-110

  Williams, Samuel ^a   Bell, Nathan ^b   Choi, Jee Whan ^c   Garland, Michael ^b   Oliker, Leonid ^a   Vuduc, Richard ^c  

^a LAWRENCE BERKELEY NATIONAL LABORATORY   (United States)

^b NVIDIA   (United States)

^c GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED ENGINEERING; SEARCH ENGINES;

COMPUTATIONAL INTENSITY; ECONOMIC MODELING; ENGINEERING COMPUTING; HIGHPERFORMANCE; MEMORY ACCESS; MULTI CORE; SPARSE MATRIX-VECTOR MULTIPLICATION; STATE-OF-THE-ART SYSTEM;

MATRIX ALGEBRA;

EID: 85017244495     PISSN: None     EISSN: None     Source Type: Book    
DOI: 10.1201/b10376     Document Type: Chapter

References (16)

1. The Open Group Base Specifications, Issue 6: POSIX Threads (pthread.h). IEEE Std 1003.1, 2004. http://www.opengroup.org/onlinepubs/009695399/basedefs/pthread.h.html.
2. NVIDIA CUDA (Compute Unified Device Architecture): Programming Guide, Version 2.1. http://developer.download.nvidia.com/compute/cuda/2_1/toolkit/docs/NVIDIA_CUDA_Programming_Guide_2.1.pdf, December 2008.
3. OpenMP: Application Program Interface, version 3.0, May 2008. http://www.openmp.org/mp-documents/spec30.pdf.
4. Muthu Manikandan Baskaran, and Rajesh Bordawekar. Optimizing sparse matrix-vector multiplication on GPUs using compile-time, and run-time strategies. Technical Report RC24704 (W0812-047), IBM T.J. Watson Research Center, Yorktown Heights, NY, USA, December 2008.
5. Nathan Bell, and Michael Garland. Implementing a sparse matrix-vector multiplication on throughput-oriented processors. In Proc. ACM/IEEE Conf. Supercomputing (SC), Portland, OR, USA, November 2009.
6. Guy E. Blelloch, Michael A. Heroux, and Marco Zagha. Segmented operations for sparse matrix computations on vector multiprocessors. Technical Report, Carnegie Mellon University, Department of Computer Science, Pittsburgh, PA, USA, August 1993.
7. Jee Whan Choi, Amik Singh, and Richard W. Vuduc. Model-driven autotuning of sparse matrix-vector multiply on GPUs. In Proc. ACM SIGPLAN Symp. Principles, and Practice of Parallel Programming (PPoPP), Bangalore, India, January 2010.
8. Eun-Jin Im, Katherine Yelick, and Richard Vuduc. Sparsity: Optimization framework for sparse matrix kernels. Int’l J. of High Performance Computing Applications (IJHPCA), 18(1): 135-158, February 2004.
9. NVIDIA. NVIDIA’s next generation CUDA compute architecture: FermiTM, v1.1. Whitepaper (electronic), September 2009. http://www.nvidia.com/content/PDF/fermi_white_papers/NVIDIA_Fermi_Compute_Architecture_Whitepaper.pdf.
10. John R. Rice, and Ronald F. Boisvert. Solving Elliptic Problems Using ELLPACK. Springer Verlag, 1984.
11. Yousef Saad. Iterative Methods for Sparse Linear Systems, Second Edition. Society for Industrial, and Applied Mathematics, April 2003.
12. Shubhabrata Sengupta, Mark Harris, Yao Zhang, and John D. Owens. Scan primitives for GPU computing. In Proc. ACM SIGGRAPH/EUROGRAPHICS Symp. Graphics Hardware, San Diego, CA, USA, 2007.
13. Richard W. Vuduc. Automatic performance tuning of sparse matrix kernels. PhD thesis, University of California, Berkeley, CA, USA, January 2004.
14. Sam Williams, Leonid Oliker, Richard Vuduc, John Shalf, Katherine Yelick, and James Demmel. Optimization of sparse matrix-vector multiplication on emerging multicore platforms. In Proc. ACM/IEEE Conf. Supercomputing (SC), 2007.
15. Sam Williams, Richard Vuduc, Leonid Oliker, John Shalf, Katherine Yelick, and James Demmel. Optimizing sparse matrix-vector multiply on emerging multicore platforms. Parallel Computing (ParCo), 35(3): 178-194, March 2009. Extends conference version: http://dx.doi.org/10.1145/1362622.1362674.
16. Samuel Webb Williams. Auto-tuning performance on multicore computers. UCB/EECS-2008-164, University of California, Berkeley, CA, USA, December 2008.