An FPGA architecture for ASIC-FPGA co-design to streamline processing of IDSs

Proceedings - 2016 International Conference on Collaboration Technologies and Systems, CTS 2016

Volumn , Issue , 2016, Pages 412-417

  Sato, Tomoaki ^a   Chivapreecha, Sorawat ^b   Moungnoul, Phichet ^b   Higuchi, Kohji ^c  

^a HIROSAKI UNIVERSITY   (Japan)

^b KING MONGKUT'S INSTITUTE OF TECHNOLOGY LADKRABANG   (Thailand)

^c UNIVERSITY OF ELECTRO COMMUNICATIONS   (Japan)

Author keywords

ASIC; ASIC FPGA co design; FPGA; IDS; Mobile devices; RTL

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; DELAY CIRCUITS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HIGH SPEED CAMERAS; LOGIC CIRCUITS; MOBILE DEVICES; MOBILE SECURITY; PIPELINE PROCESSING SYSTEMS;

ARITHMETIC CIRCUIT; CO-DESIGNS; FPGA ARCHITECTURES; HIGH-SPEED PROCESSING; LOW-POWER OPERATION; PARALLEL PROCESSING; PROCESSING CAPACITIES; UNAUTHORIZED ACCESS;

INTEGRATED CIRCUIT DESIGN;

EID: 85017036836     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CTS.2016.77     Document Type: Conference Paper

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