Modeling and characterization of SIPOS passivated, high voltage, N- and P-channel lateral resurf type DMOSFETs

Proceedings of the International Symposium on Power Semiconductor Devices and ICs

Volumn 1992-May, Issue , 1992, Pages 288-292

  Sakai, T ^a   So, K C ^a   Shen, Z ^a   Chow, T P ^a  

^a RENSSELAER POLYTECHNIC INSTITUTE   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DMOSFET; HIGH VOLTAGE; P CHANNELS; TWO DIMENSIONAL DEVICE SIMULATORS;

SEMICONDUCTOR DEVICES;

EID: 85014937772     PISSN: 10636854     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISPSD.1992.991288     Document Type: Conference Paper

References (11)

1. M. Hoshi, T. Mihara, T. Matsushita and Y. Hirota, "Low On-resistance Power LDMOSFET Using Double Metal Process Technology, " in Proc. 3rd ISPSD, 1991, pp. 61-64.
2. J. A. Appels and H. M. J. Vaes, "High Voltage Thin Layer Devices (RESURF Devices), " in IEDM Tech. Dig., 1979, pp. 238-241.
3. A. Nakagawa, N. Yasuhara and Y. Baba, "Breakdown Voltage Enhancement for Devices on Thin Silicon Layer/Silicon Dioxide Film, " IEEE Trans. Electron Devices, vol. 38, pp. 1650-1654, 1991.
4. S. Mukherjee, C. J. Chou, K. Shaw, D. McArthur and V. Rumennik, "The Effects of SIPOS Passivation on DC and Switching performance of High Voltage MOS Transistors, " in IEDM Tech. Dig., 1986, pp. 646-649.
5. T. P. Chow, D. N. Pattanayak, B. J. Baliga and M. S. Adler, "The Effect of SIPOS on the Performance of Lateral Insulated Gate Bipolar Transistors, " IEEE Trans. Electron Devices, vol. ED-34, p. 2359, 1987.
6. T. Stockmeier and K. Lilja, "SIPOS-Passivation for High Voltage Power Devices with Planar Junction Termination, " in Proc. 3rd ISPSD, 1991, pp. 145-148.
7. H. M. J. Vaes and J. A. Appels, "High Voltage, High Current Lateral Devices, " in IEDM Tech. Dig., 1980, pp. 87-90.
8. H. Mochizuki, T. Aoki, H. Yamoto, M. Okayama, M. Abe and T. Ando, "Semi-Insulating Polycrystalline-Silicon (SIPOS) Films Applied to MOS Integrated Circuits, " in Proc. 7th Conf. on Solid State Devices, Tokyo, 1975, pp. 41-48.
9. D. M. Taylor and D. W. Tong, "Density of States at the Interface between Semi-Insulating Polycrystalline and Single Crystal Silicon, " J. Appl. Phys., vol. 56, pp. 1881-1883, 1984.
10. J. N. Sandoe, J. R. Hughes and J. A. G. Slatter, "Characterisation and Modelling of SIPOS on Silicon High-Voltage Devices, " IEE Proceedings, vol. 132, Pt. I, pp. 281-284, 1985.
11. D. W. Tong, J. L. Benjamin and W. R. Van Dell, "Interface Effects of SIPOS Passivation, " IEEE Trans. Electron Devices, vol. ED-33, pp. 779-787, 1986.