Near-Threshold RISC-V core with DSP extensions for scalable IoT endpoint devices

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 25, Issue 10, 2017, Pages 2700-2713

  Gautschi, Michael ^a   Schiavone, Pasquale Davide ^a   Traber, Andreas ^a,b   Loi, Igor ^d   Pullini, Antonio ^a   Rossi, Davide ^d   Flamand, Eric ^a,d   Gürkaynak, Frank K ^a   Benini, Luca ^a,c  

^a ETH ZURICH   (Switzerland)

^b Advanced Circuit Pursuit AG   (Switzerland)

^c UNIVERSITY OF BOLOGNA   (Italy)

^d Greenwaves Technologies SAS   (France)

Author keywords

Instruction set architecture (ISA) extensions; Internet of Things; Multicore; RISC V; Ultralow power (ULP)

Indexed keywords

DATA HANDLING; DIGITAL SIGNAL PROCESSING; DIGITAL STORAGE; INTERNET OF THINGS; MEMORY ARCHITECTURE;

COMPUTATIONAL DENSITY; COMPUTING CAPABILITY; INSTRUCTION EXTENSIONS; MICRO-ARCHITECTURAL OPTIMIZATION; MULTI-CORE CLUSTER; PERFORMANCE SCALABILITY; SENSOR PROCESSING; SINGLE INSTRUCTION MULTIPLE DATA;

ENERGY EFFICIENCY;

EID: 85014217863     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2017.2654506     Document Type: Article

References (46)

1. G. Lammel, "The future of MEMS sensors in our connected world," in Proc. Int. Conf. Micro Electro Mech. Syst., 2015, pp. 61-64.
2. V. Shnayder, M. Hempstead, B.-R. Chen, G. W. Allen, and M. Welsh, "Simulating the power consumption of large-scale sensor network applications," in Proc. 2nd Int. Conf. Embedded Netw. Sens. Syst. (SenSys), Nov. 2004, pp. 188-200.
3. E. F. Nakamura, A. A. F. Loureiro, and A. C. Frery, "Information fusion for wireless sensor networks: Methods, models, and classifications," ACM Comput. Surv., Vol. 39, no. 3, 2007, Art. no. 9.
4. M. Konijnenburg et al., "A battery-powered efficient multi-sensor acquisition system with simultaneous ECG, BIO-Z, GSR, and PPG," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Jan. 2016, pp. 480-482.
5. F. Zhang et al., "A batteryless 19 μ W MICS/ISM-band energy harvesting body area sensor node So C," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Vol. 55. Feb. 2012, pp. 298-299.
6. S. R. Sridhara et al., "Microwatt embedded processor platform for medical system-on-chip applications," IEEE J. Solid-State Circuits, Vol. 46, no. 4, pp. 721-730, Apr. 2011.
7. R. G. Dreslinski, M. Wieckowski, D. Blaauw, D. Sylvester, and T. Mudge, "Near-threshold computing: Reclaiming Moore's law through energy efficient integrated circuits," Proc. IEEE, Vol. 98, no. 2, pp. 253-266, Feb. 2010.
8. A. Y. Dogan, J. Constantin, D. Atienza, A. Burg, and L. Benini, "Lowpower processor architecture exploration for online biomedical signal analysis," IET Circuits, Devices Syst., Vol. 6, no. 5, pp. 279-286, 2012.
9. R. Banakar, S. Steinke, B.-S. Lee, M. Balakrishnan, and P. Marwedel, "Scratchpad memory: Design alternative for cache on-chip memory in embedded systems," in Proc. 10th Int. Symp. Hardw./Softw. Codesign, May 2002, pp. 73-78.
10. A. Teman, D. Rossi, P. Meinerzhagen, L. Benini, and A. Burg, "Power, area, and performance optimization of standard cell memory arrays through controlled placement," ACM Trans. Design Autom. Electron. Syst., Vol. 21, no. 4, Sep. 2016, Art. no. 59.
11. A. Waterman et al., "The RISC-V instruction set manual, volume I: Base user-level ISA," Dept. Elect. Eng. Comput. Sci., Univ. California, Berkeley, Berkeley, CA, USA, Tech. Rep. UCB/EECS-2011-62, 2011.
12. O. Azizi et al., "Energy-performance tradeoffs in processor architecture and circuit design: A marginal cost analysis," in Proc. ISCA, 2010, pp. 26-36.
13. STMicroelectronics. STM32F Datasheet, accessed on Oct. 10, 2016. [Online]. Available: http://www.st.com/resource/en/datasheet/stm32f405og.pdf
14. Ambiqmicro. Apollo Datasheet, accessed on Oct. 16, 2016. [Online]. Available: https://www.eembc.org/ulpbench/Apollo-MCU-Data-SheetDS0010V0p90.pdf
15. NXP. LPC5410× Product Data Sheet, accessed on Sep. 25, 2016. [Online]. Available: http://www.nxp.com/documents/data-sheet/LPC5410X.pdf
16. S. Rele, S. Pande, S. Onder, and R. Gupta, "Optimizing static power dissipation by functional units in superscalar processors," in Proc. Int. Conf. Compiler Construction, 2002, pp. 261-275.
17. N. Ickes, Y. Sinangil, F. Pappalardo, E. Guidetti, and A. P. Chandrakasan, "A 10 pJ/cycle ultra-low-voltage 32-bit microprocessor system-on-chip," in Proc. Eur. Solid-State Circuits Conf., Sep. 2011, pp. 159-162.
18. B. Zhai et al., "Energy-efficient subthreshold processor design," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., Vol. 17, no. 8, pp. 1127-1137, Aug. 2009.
19. G. Gammie et al., "A 28 nm 0.6 V low power DSP for mobile applications," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2011, pp. 132-133.
20. MAX tracking," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Vol. 57. Feb. 2014, pp. 452-453.
21. D.-H. Le, N. Sugii, S. Kamohara, X.-T. Nguyen, K. Ishibashi, and C.-K. Pham, "Design of a low-power fixed-point 16-bit digital signal processor using 65nm SOTB process," in Proc. Int. Conf. IC Design Technol. (ICICDT), Jun. 2015, pp. 1-4.
22. "ARM cortex M-4 technical reference manual," ARM, Cambridge, U.K., Tech. Rep., 2015.
23. A. A. Faroqui and V. G. Oklobdzija, "Impact of architecture extensions for media signal processing on data-path organization," in Proc. Conf. Rec. 34th Asilomar Conf. Signals, Syst. Comput., Oct. 2000, pp. 1679-1683.
24. X. Zhang, Z. Li, and Q. Zheng, "Design of a configurable fixed-point multiplier for digital signal processor," in Proc. Asia Pacific Conf. Postgraduate Res. Microelectron. Electron., PrimeAsia, Jan. 2009, pp. 217-220.
25. N. Ickes, D. Finchelstein, and A. P. Chandrakasan, "A 10-pJ/instruction, 4-MIPS micropower DSP for sensor applications," in Proc. IEEE Asian Solid-State Circuits Conf. (A-SSCC), Nov. 2008, pp. 289-292.
26. W. Qadeer, R. Hameed, O. Shacham, P. Venkatesan, C. Kozyrakis, and M. A. Horowitz, "Convolution engine: Balancing efficiency & flexibility in specialized computing," ACM SIGARCH Comput. Archit. News, Vol. 41, no. 3, pp. 24-35, 2013.
27. L. Cavigelli and L. Benini, "A 803 GOp/s/W convolutional network accelerator," IEEE Trans. Circuits Syst. Video Technol., Vol. PP, no. 99, p. 1, doi: 10.1109/TCSVT.2016.2592330.
28. F. Conti and L. Benini, "A ultra-low-energy convolution engine for fast brain-inspired vision in multicore clusters," in Proc. DATE, Mar. 2015, pp. 683-688.
29. Texas Instruments. CC2650 SimpleLink Multistandard Wireless MCU, accessed on Sep. 12, 2016. [Online]. Available: http://www.ti.com/lit/ds/symlink/cc2650.pdf
30. N. Neves, N. Sebastião, D. Matos, P. Tomás, P. Flores, and N. Roma, "Multicore SIMD ASIP for next-generation sequencing and alignment biochip platforms," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., Vol. 23, no. 7, pp. 1287-1300, Jul. 2015.
31. S. Hsu et al., "A 280mV-to-1.1V 256b reconfigurable SIMD vector permutation engine with 2-dimensional shuffle in 22nm CMOS," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2012, pp. 178-180.
32. D. Fick et al., "Centip3De: A cluster-based NTC architecture with 64 ARM cortex-M3 cores in 3D stacked 130 nm CMOS," IEEE J. SolidState Circuits, Vol. 48, no. 1, pp. 104-117, Jan. 2013.
33. D. Rossi et al., "A 60 GOPS/W, 1.8 V to 0.9 V body bias ULP cluster in 28 nm UTBB FD-SOI technology," Solid State Electron., Vol. 117, pp. 170-184, Mar. 2016.
34. D. Rossi et al., "193 MOPS/mW 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing," in Proc. IEEE Symp. Low-Power High-Speed Chips (COOL CHIPS), Apr. 2016, pp. 1-3.
35. A. Pullini, F. Conti, D. Rossi, I. Loi, M. Gautschi, and L. Benini, "A heterogeneous multi-core system-on-chip for energy efficient brain inspired vision," in Proc. ISCAS, May 2016, p. 2910.
36. M. Sonka, V. Hlavac, and R. Boyle, Image Processing, Analysis and Machine Vision. New York, NY, USA: Springer, 1993, doi: 10.1007/9781-4899-3216-7.
37. I. Loi, D. Rossi, G. Haugou, M. Gautschi, and L. Benini, "Exploring multi-banked shared-L1 program cache on ultra-low power, tightly coupled processor clusters," in Proc. 12th ACM Int. Conf. Comput. Frontiers, May 2015, Art. no. 64.
38. G.-R. Uh, Y. Wang, D. Whalley, S. Jinturkar, C. Burns, and V. Cao, "Techniques for effectively exploiting a zero overhead loop buffer," in Proc. Int. Conf. Compiler Construction, 2000, pp. 157-172.
39. R. S. Bajwa et al, "Instruction buffering to reduce power in processors for signal processing," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., Vol. 5, no. 4, pp. 417-424, Dec. 1997.
40. R. B. Lee, "Subword parallelism with MAX-2," IEEE Micro, Vol. 16, no. 4, pp. 51-59, Aug. 1996.
41. A. Shahbahrami, B. Juurlink, and S. Vassiliadis, "A comparison between processor architectures for multimedia application," in Proc. 15th Annu. Workshop Circuits, Syst. Signal Process., ProRisc, 2004, pp. 138-152.
42. H. Chang, J. Cho, and W. Sung, "Performance evaluation of an SIMD architecture with a multi-bank vector memory unit," in Proc. IEEE Workshop Signal Process. Syst. Design Implement. (SIPS), Oct. 2006, pp. 71-76.
43. C.-H. Chang, S.-H. Chen, B.-W. Chen, W. Ji, K. Bharanitharan, and J.-F. Wang, "Fixed-point computing element design for transcendental functions and primary operations in speech processing," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., Vol. 24, no. 5, pp. 1993-1997, May 2016.
44. B. Parhami, "Variations on multioperand addition for faster logarithmic-time tree multipliers," in Proc. Conf. Rec. 30th Asilomar Conf. Signals, Syst. Comput., Nov. 1996, pp. 899-903.
45. D. Rossi, I. Loi, F. Conti, G. Tagliavini, A. Pullini, and A. Marongiu, "Energy efficient parallel computing on the PULP platform with support for Open MP," in Proc. IEEE 28th Conv. Elect. Electron. Eng. Israel (IEEEI), Dec. 2014, pp. 1-5.
46. M. Gautschi et al., "Tailoring instruction-set extensions for an ultra-low power tightly-coupled cluster of OpenRISC cores," in Proc. IFIP/IEEE Int. Conf. Very Large Scale Integr. (VLSI-SoC), Oct. 2015, pp. 25-30.