Demystifying Switched Capacitor Circuits

Demystifying Switched Capacitor Circuits

Volumn , Issue , 2006, Pages

  Liu, Mingliang ^a  

^a Rowland Heights   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 85013723947     PISSN: None     EISSN: None     Source Type: Book    
DOI: 10.1016/B978-0-7506-7907-7.X5011-0     Document Type: Book

References (284)

1. Chen J.-Y. MOS devices and technologies for VLSI 1990, Prentice Hall.
2. Tsividis Y. Operation and modeling of the MOS transisto 1999, McGraw-Hill, Englewood Cliffs, NJ. 2nd Ed.
3. Lee T.H. The design of CMOS radio-frequency integrated circuits 1998, Cambridge University Press, New York.
4. Dennard R.H., et al. Design of ion-implanted MOSFET's with very small physical dimensions. IEEE Journal of Solid-State Circuits October 1974, Vol. 9(No. 5):256-268.
5. Hu C. IC reliability simulation. IEEE Journal of Solid-State Circuits March 1992, Vol. 27(No. 3):241-246.
6. Gregorian R., Temes G.C. Analog MOS integrated circuits for signal processing 1986, John Wiley & Sons, Cambridge, UK.
7. Wegmann G., Vittoz E.A., Rahali F. Charge injection in analog MOS switches. IEEE Journal of Solid-State Circuits December 1987, Vol. SC-22(No. 6):1091-1097.
8. Sheu B., Shieh J., Patil M. Modeling charge injection in MOS analog switches. IEEE Trans. on Circuits and Systems February 1987, Vol. CAS-34(No. 2):214-216.
9. McCreary J., Gray P.R. All MOS charge redistribution analog-to-digital conversion techniques-Part 1. IEEE Journal of Solid-State Circuits December 1975, Vol. SC-10(No. 6):371-379.
10. Sze S.M. Semiconductor devices, physics and technology 1985, John Wiley & Sons, New York.
11. Hastings A. The art of analog layout 2005, Prentice Hall, New York. 2nd Ed.
12. Gray P.R., Meyer R.G. Analysis and design of analog integrated circuits 1993, John Wiley & Sons, Englewood Cliffs, NJ.
13. Johns D.A., Martin K. Analog integrated circuits design 1997, John Wiley & Sons, New York.
14. Nicollini G., Confalonieri P., Senderowicz D. A fully differential sample-and-hold circuit for high-speed applications. IEEE Journal of Solid-State Circuits October 1989, Vol. 24:1461-1465.
15. Sooch N., AT&T Bell Lab. MOS cascode current mirror 1985, U.S. Patent 4550284.
16. Bult K., Geelen G. A fast-settling CMOS Op Amp for SC circuits with 90-dB DC gain. IEEE Journal of Solid-State Circuits December 1990, Vol. 25:1379-1383.
17. Brodersen R.W., Gray P.R., Hodges D.A. MOS Switched-capacitor filters. Proceedings of IEEE January 1979, Vol. 67:61-75.
18. McKinney J.A., Halijak C.A. The periodically reverse-switched capacitor. IEEE Trans. on Circuits & Systems September 1968, Vol. CT-15(No. 3):288-290.
19. Temes G.C. The derivation of switched-capacitor filters from active RC prototypes. Electronics Letters June 1978, Vol. 14(No. 3):361-362.
20. Temes G.C., Orchard H.J., Jahanbegloo M. Switched-capacitor filter design using the bilinear z-transform. IEEE Trans. on Circuits & Systems December 1978, Vol. CAS-25(No. 12):1039-1044.
21. McCreary J.L. Matching properties, and voltage and temperature dependence of MOS capacitors. IEEE Journal of Solid-State Circuits December 1981, Vol. SC-16(No. 6):608-616.
22. Fried D. Analog sample-data filters. IEEE Journal of Solid-State Circuits August 1972, Vol. SC-7(No. 4):302-304.
23. Temes G.C., Young I.A. An improved switched-capacitor integrator. Electronics Letters April 1978, Vol. 14(No. 9):287-288.
24. Jacobs G.M., Allstot D.J., Brodersen R.W., Gray P.R. MOS switched-capacitor ladder filters. IEEE Trans. on Circuits & Systems December 1978, Vol. CAS-25(No. 12):1014-1021.
25. Martin K. Improved circuits for the realization of switched capacitor filters. IEEE Trans. on Circuits & Systems April 1980, Vol. CAS-27(No. 4):237-244.
26. Hosticka B.J., Moschytz G.S. Practical design of switched capacitor networks for integrated circuit implementation. IEE Electronics Circuits and Systems March 1979, Vol. 3:76-88.
27. Vittoz E.A. The design of high-performance analog circuits on digital CMOS chips. IEEE Journal of Solid-State Circuits June 1985, Vol. SC-20(No. 3):657-665.
28. Sedra A.S., Brackett P.O. Filter theory and design: Active and passive 1978, Matrix Publishers, New York.
29. Fleischer P.E., Laker K.R. A family of active switched capacitor biquad building blocks. The Bell Systems Technical Journal April 1979, No. 58:2235-2269.
30. Signell S. On selectivity properties of discrete-time linear networks. IEEE Trans. on Circuits & Systems March 1984, Vol. CAS-31(No. 3):275-280.
31. Ki W-H., Temes G.C. Optimal capacitance assignment of switched-capacitor biquads. IEEE Trans. on Circuits & Systems I: Fundamental Theory and Applications June 1995, Vol. CAS-42(No. 6):334-342.
32. Allstot D.J., Brodersen R.W., Gray P.R. An electrically-programmable switched capacitor filter. IEEE Journal of Solid-State Circuits December 1979, Vol. SC-14(No. 6):1034-1041.
33. Cox D.B., Lin L.T., Florek R., Tseng H.F. A real-time programmable switched capacitor filter. IEEE Journal of Solid-State Circuits December 1980, Vol. SC-15(No. 6):972-977.
34. Signell S. A bilinear switched capacitor bandpass filter with independent selectivity and center frequency adjustments. IEEE International Symposium on Circuits and Systems May 1984, 802-804.
35. Allen P.E., Sanchez-Sinencio E. Switched capacitor circuits 1984, Van Nostrand, Beaverton, OR.
36. Gregorian R., Temes G.C. Analog MOS integrated circuits for signal processing 1986, John Wiley & Sons, New York.
37. Schauman R., Ghausi M., Laker K. Design of analog filters passive, active RC, and switched capacitor 1990, Prentice Hall, New York.
38. Bruton L.T. Low sensitivity digital ladder filters. IEEE Trans. on Circuits & System March 1975, Vol. CAS-22(No. 3):168-176.
39. http://www.cisl.Columbia.edu/projects/switcap.
40. Knob A. Novel stray-insensitive switched-capacitor integrator realizing the bilinear z-transform. Electronics Letters February 1980, Vol. 16(No. 5):173-174.
41. Fleischer P.E., Ganesan A., Laker K. Parasitic compensated switched capacitor circuits. Electronics Letters 1981, Vol. 17(No. 14):929-931.
42. Eriksson S., Akhlaghi H. Noninverting parasitic-compensated bilinear SC integrator with only one amplifier. Electronics Letters April 1983, Vol. 19(No. 2):450-452.
43. Norsworthy S.R., Schreier R., Temes G.C. Delta-sigma data converters: Theory, design and simulation 1997, IEEE Press, Englewood Cliffs, NJ.
44. Brooks T., et al. A cascased sigma-delta pipeline A/D converter with 1.25 MHz signal bandwidth and 89 dB SNR. IEEE Journal of Solid-State Circuits 1997, Vol.32(No. 12):1896-1906. December.
45. Ribner D.B., et al. A third-order multistage sigma-delta modulator with reduced sensitivity to nonidealities. IEEE Journal of Solid-State Circuits December 1991, Vol. 26(No. 12):1764-1774.
46. Maloberti F., et al. Bilinear design of fully differential switched-capacitor ladder filters. IEE Proceeding Electronic Circuits & Systems 1985, No. 132:266-272.
47. Senderowicz D., et al. Low-voltage double-sampled ΣΔ converters. IEEE Journal of Solid-State Circuits December 1997, Vol. 32(No. 12):1907-1912.
48. Nagaraj K. A parasitic-insensitive area-efficient approach to realizing very large time constants in switched-capacitor circuits. IEEE Trans. on Circuits & Systems September 1989, Vol. CAS-36(No. 9):1210-1216.
49. Ki W-H., Temes G.C. Area-efficient gain- and offset-compensated very-large-time-constant SC biquads. IEEE International Symposium on Circuits and Systems May 1992, No. 3:1187-1190. San Diego, CA.
50. Tewksbury S., et al. Terminology related to the performance of S/H, A/D, and D/A circuits. IEEE Trans. on Circuits & Systems July 1978, Vol. CAS-25(No. 7):419-426.
51. Shinagawa M., et al. Jitter analysis of high speed sampling systems. IEEE Journal of Solid-State Circuits February 1990, Vol. 25(No. 1):220-224.
52. Shieh J., Patil M., Sheu B. Measurement and analysis of charge injection in MOS analog switches. IEEE Journal of Solid-State Circuits April 1987, Vol. 22(No. 2):277-281.
53. Geiger R., Allen P., Strader N. VLSI: Design techniques for analog and digital circuits 1990, McGraw-Hill, New York.
54. van de Plassche R. Integrated analog-to-digital and digital-to-analog data converters 1994, Kluwer Academic Publisher, New York.
55. Kuyel T. Method and system for measuring jitter 2003, U.S. Patent 6640193.
56. Zanchi A., et al. Measurement and spice prediction of sub-picosecond clock jitter in A-to-D converters. IEEE International Symposium on Circuits and Systems May 2003, Vol. 4:557-560. Bangkok, Thailand.
57. Razavi B. Principles of data conversion system design 1995, IEEE Press, Berlin, Germany.
58. Hadidi K., et al. An open-loop full CMOS 103MHz -61 dB THD S&H circuit. Proceedings of the IEEE Custom Integrated Circuits Conference May 1998, Vol. 3:381-383.
59. Boni A., et al. A 10-b 185-MS/s track-and-hold in 0.35 μm CMOS. IEEE Journal of Solid-State Circuits February 2001, Vol. 36(No. 2):195-203.
60. Abo A., Gray P.R. A 1.5-V 10-bit 14.3-MS/s CMOS pipeline analog-to-digital converter. IEEE Journal of Solid-State Circuits May 1999, Vol. 34(No. 5):599-606.
61. Pregardier B., et al. A 1.2-GS/s silicon bipolar track & hold IC. IEEE Journal of Solid-State Circuits September 1996, Vol. 31(No. 9):1336-1339.
62. Baumheinrich T., et al. A 1-GSample/s 10-b full Nyquist silicon bipolar track and hold IC. IEEE Journal of Solid-State Circuits December 1997, Vol. 32(No. 12):1951-1959.
63. Nayebi M., Wooley B.A. A 10-bit video BiCMOS track-and-hold amplifier. IEEE Journal of Solid-State Circuits December 1989, Vol. 24(No. 12):1507-1516.
64. Wang F., Temes G.C. A fast offset-free S/H circuit. IEEE Journal of Solid-State Circuits October 1988, Vol. SC-23(No. 5):1270-1272.
65. Lim P.J., Wooley B.A. A high-speed sample-and-hold technique using a Miller hold capacitance. IEEE Journal of Solid-State Circuits April 1991, Vol. 26(No. 4):643-651.
66. Temes G.C., et al. A high-frequency T/H stage with offset and gain compensation. IEEE Trans. on Circuits & Systems August 1995, Vol. CAS-42(No. 8):559-561.
67. Yang W., et al. A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquist input. IEEE Journal of Solid-State Circuits December 2001, Vol. 36(No. 12):1931-1936.
68. Crols J., Steyaert M. Switched-opamp: an approach to realize full CMOS switched-capacitor circuits at very low power supply voltages. IEEE Journal of Solid-State Circuits August 1994, Vol. 29(No. 8).
69. Gregorian R., Nicholson W.E. Switched-capacitor decimation and interpolation circuits. IEEE Trans. on Circuits & Systems June 1980, Vol. CAS-27(No. 6):509-514.
70. Senderowicz D., et al. PCM Telephony: Reduced architecture for a D/A converter and filter combination. IEEE Journal of Solid-State Circuits August 1990, Vol. 25(No. 8):987-995.
71. Adams R., et al. A 113 dB SNR oversampling DAC with segmented noise-shaped scrambling. IEEE Journal of Solid-State Circuits December 1998, Vol. 33(No. 12):1871-1878.
72. Hsu T.-H. Improved design techniques for switched-capacitor ladder filters. Ph.D. dissertation 1982, UCLA, Piscataway, NJ.
73. Unbehauen R., Cichocki A. MOS switched-capacitor and continous-time integrated circuits and systems 1989, Springer-Verlag, Los Angles, CA.
74. Seng-Pan U., Martins R.P., Franca J.E. Improved switched-capacitor interpolators with reduced sample-and-hold effects. IEEE Trans. on Circuits & Systems II August 2000, Vol. 47(No. 8):665-684.
75. von Grunigen D., et al. Integrated switched-capacitor low-pass filter with combined anti-aliasing decimation filter for low frequencies. IEEE Journal of Solid-State Circuit December 1982, Vol. SC-17(No. 6):1024-1029.
76. Franca J.E., Martins R.P. IIR switched-capacitor decimator building blocks with optimum implementation. IEEE Trans. on Circuits and Systems January 1990, Vol. 37(No. 1):81-90.
77. Lindfors S., et al. A 3-V 230-MHz CMOS decimation subsampler. IEEE Trans. on Circuits and Systems II March 2003, Vol. 50(No. 3):105-117.
78. Mason S., Zimmermann H. Electronic circuits, signals and systems 1960, John Wiley & Sons, Berlin, Germany.
79. Fried D. Analog sample-data filters. IEEE Journal of Solid-State Circuits August 1972, Vol. SC-7(No. 4):302-304.
80. Brodersen R.W., Gray P.R., Hodges D.A. MOS Switched-capacitor filters. Proceedings of IEEE January 1979, Vol. 67:61-75.
81. Fleischer P.E., Laker K.R. A family of active switched capacitor biquad building blocks. The Bell Systems Technical Journal 1979, No. 58:2235-2269.
82. Martin K. Improved circuits for the realization of switched-capacitor filters. IEEE Trans. on Circuits and Systems April 1980, Vol. CAS-27(No. 4):237-244.
83. Martin K., Sedra A.S. Exact design of switched-capacitor bandpass filters using coupled-biquadstructures. IEEE Trans. on Circuits and Systems June 1980, Vol. CAS-27(No. 6):469-478.
84. Laker K.R., Sansen W. Design of analog integrated circuits and systems 1994, McGraw-Hill, New York.
85. Jou I.C., Wu C.Y., Liu R.L. The characteristic comparison of fully differential switched capacitor biquads. Proceedings of IEEE International Symposium on Circuits and Systems May 1989, Vol. III:1712-1715. Portland, OR.
86. Choi T., et al. High-frequency CMOS switched-capacitor filters for communications application. IEEE Journal of Solid-State Circuits December 1983, Vol. SC-18(No. 6):652-664.
87. Huang Q. A novel technique for the reduction of capacitance spread in high Q SC circuits. Proceedings of IEEE International Symposium on Circuits and Systems June 1988, Vol. II:1249-1252. Helsinki, Finland.
88. Nagaraj K., et al. Switched-capacitor circuits with reduced sensitivity to amplifier gain. IEEE Trans. on Circuits and Systems May 1987, Vol. CAS-34(No. 5):571-574.
89. Jacobs G.M., Allstot D.J., Brodersen R.W., Gray P.R. Design techniques for MOS switched-capacitor ladder filters. IEEE Trans. on Circuits and Systems December 1978, Vol. CAS-25(No. 12):1014-1021.
90. Fettweis A., et al. MOS switched capacitor filters using voltage inverter switches. IEEE Trans. on Circuits and Systems June 1980, Vol. CAS-27(No. 6):527-538.
91. Montecchi F. On design of switched-capacitor filters with the voltage-inverter-switch approach. Proceedings of IEEE International Symposium on Circuits and Systems June 1988, Vol. II:1479-1482. Helsinki, Finland.
92. Gregorian R., Temes G.C. Analog MOS integrated circuits for signal processing 1986, John Wiley & Sons, New York.
93. Temes G.C. Switched-capacitor filters. Class notes: Analog CMOS integrated circuit design 2002, Oregon State University, New York.
94. Ki W.-H., Temes G.C. Optimal capacitance assignment of switched-capacitor biquads. IEEE Trans. on Circuits and Systems June 1995, Vol. 42(No. 6):334-342.
95. Temes G.C. Finite amplifier gain and bandwidth effect in switched-capacitor filters. IEEE Journal of Solid-State Circuits June 1980, Vol. SC-15(No. 3):358-361.
96. Martin K., Sedra A.S. Effects of the op-amp finite gain and bandwidth on the performance of switched-capacitor filters. IEEE Trans. Circuits and Systems August 1981, Vol. CAS-28(No. 8):822-829.
97. Johns D.A., Martin K. Analog integrated circuits design 1997, John Wiley & Sons, Corvallis, OR.
98. Fan S.C., et al. Switched-capacitor filters using unit-gain buffers. Proceedings of IEEE International Symposium on Circuits and Systems May 1980, 334-337.
99. Fischer G., Moschytz G. On the frequency limitations of SC filters. IEEE Journal of Solid-State Circuits August 1984, Vol. SC-19(No. 4):510-518.
100. Larson L.E. GaAs switched-capacitor circuits for high-speed signal processing. IEEE Journal of Solid-State Circuits December 1987, Vol. SC-22(No. 6):971-981.
101. Op't Eynde F., Sansen W.C. Design and optimisation of CMOS wideband amplifiers. Proceedings of IEEE Custom Integrated Circuits Conference May 1989, 25.7.1-25.7.4. San Diego, Ca.
102. Op't Eynde F., Sansen W.C. A CMOS wideband amplifier with 800 MHz gain-bandwidth. Proceedings of IEEE Custom Integrated Circuits Conference May 1991, 9.1.1-9.1.4. San Diego, CA.
103. Baschirotto A., Severi F., Castello R. A 200-Ms/s 10-mW switched-capacitor filter in 0.5μm CMOS technology. IEEE Journal of Solid-State Circuits August 2000, Vol. 35(No. 8):1215-1219.
104. Plaza A.D. High-frequency switched-capacitor filter using unity-gain buffers. IEEE Journal of Solid-State Circuits June 1986, Vol. SC-21:470-477.
105. Wu P. Unit-gain buffer switched-capacitor filters-design techniques and circuit analysis. Ph.D. dissertation 1986, University of California, New York.
106. Wu C.Y., Lu P.H., Tsai M.K. Design techniques for high-frequency CMOS switched-capacitor filters using non-op-amp-based unity-gain amplifiers. IEEE Journal of Solid-State Circuits October 1991, Vol. 26:1460-1466.
107. Gray P.R., Meyer R. Future directions of silicon ICs for RF personal communications. Proceedings of the IEEE Custom Integrated Circuits Conference May 1995, 83-90.
108. Abidi A.A., et al. The future of CMOS wireless transceivers. IEEE Solid-State Circuits Conference, Digest of Technical Papers February 1997, 118-119.
109. UWB: Theory and applications 2004, John Wiley & Sons, Los Angeles, CA. I. Oppermann (Ed.).
110. Fujimori I., et al. A 90-dB SNR 2.5-MHz output-rate ADC using cascaded multibit delta-sigma modulation at 8x oversampling. IEEE Journal of Solid-State Circuits July 1999, Vol. 35:1820-1828.
111. Geerts Y., et al. A 3.3-V, 15-bit, delta-sigma ADC with a signal bandwidth of 1.1 MHz for ADSL applications. IEEE Journal of Solid-State Circuits July 1999, Vol. 34:927-936.
112. Vleugels K., et al. A 2.5-V sigma-delta modulator for wideband communication applications. IEEE Journal of Solid-State Circuits December 2001, Vol. 36:1887-1898.
113. Wang X., Moon U., Liu M., Temes G.C. Digital correlation technique for the estimation and correction of DAC errors in multibit MASH AX ADCs. Proceedings of IEEE International Symposium on Circuits and Systems May 2002, Vol. IV:691-694. Phoenix, AZ.
114. Tewksbury S., et al. Terminology related to the performance of S/H, A/D, and D/A circuits. IEEE Trans. on Circuits & Systems July 1978, Vol. CAS-25(No. 7):419-426.
115. van de Plassche R. Integrated analog-to-digital and digital-to-analog data converters 1994, Kluwer Academic Publisher, New York.
116. Razavi B. Principles of data conversion system design 1995, IEEE Press, Berlin, Germany.
117. Johns D.A., Martin K. Analog integrated circuits design 1997, John Wiley & Sons, Piscataway, NJ.
118. IEEE standard for performance measurements of A/D and D/A converters for PCM television video circuits 1984, IEEE Std. 746-1984, IEEE Press, New York.
119. IEEE standard for terminology and test methods for analog-to-digital converters 2001, IEEE Std. 1241-2000, IEEE Press, New York.
120. Holloway P. A trimless 16-bit digital potentiometer. IEEE Solid-State Circuits Conference, Digest of Technical Papers February 1984, 66-67.
121. Abrial A., et al. A 27-MHz digital-to-analog video processor. IEEE Journal of Solid-State Circuits December 1988, Vol. SC-23(No. 6):1358-1369.
122. Miki T., et al. An 80-MHz 8-bit CMOS D/A converter. IEEE Journal of Solid-State Circuits December 1986, Vol. SC-21(No. 6):983-988.
123. Schouwenaars H., Groeneveld D., Termeer H. A low-power stereo 16-bit CMOS D/A converter for digital audio. IEEE Journal of Solid-State Circuits December 1988, Vol. SC-23(No. 6):1290-1297.
124. Groeneveld D., et al. A self-calibration technique for monolithic high-resolution D/A converters. IEEE Journal of Solid-State Circuits December 1989, Vol. SC-24(No. 6):1517-1522.
125. Mercer D., Singer L. 12-bit 125-MS/s CMOS D/A designed for spectral performance. Proceedings of International Symposium on Low Power Electronics and Design 1996, Vol. 2:243-246. No. 1, August.
126. Hester R., et al. CODEC for echo-canceling full-rate ADSL modems. IEEE Solid-State Circuits Conference, Digest of Technical Papers February 1999, 242-243.
127. Bugeja A., et al. A self-trimming 14-b 100-MS/s CMOS DAC. IEEE Journal of Solid-State Circuits December 2000, Vol. 35(No. 12):1841-1852.
128. Martin K., et al. A differential switched-capacitor amplifier. IEEE Journal of Solid-State Circuits February 1987, Vol. SC-22:104-106.
129. Matsumoto H., Watanabe K. Spike-free switched-capacitor circuits. Electronics Letters April 1987, Vol. 23:428-429.
130. Matsumoto H., Watanabe K. Switched-capacitor algorithmic digital-to-analog converters. IEEE Trans. on Circuits & Systems 1986, Vol. CAS-33:721-724.
131. Shih C.C., Gray P.R. Reference refreshing cyclic analog-to-digital and digital-to-analog converters. IEEE Journal of Solid-State Circuits August 1986, Vol. 21:544-554.
132. Li P., et al. A ratio-independent algorithmic analog-to-digital conversion technique. IEEE Journal of Solid-State Circuits December 1984, Vol. 19:828-836.
133. Onodera H., et al. A cyclic A/D converter that does not require ratio-matched components. IEEE Journal of Solid-State Circuits February 1988, Vol. 23:152-158.
134. Chin S.Y., Wu C.Y. A CMOS ratio-independent and gain-insensitive algorithmic analog-to-digital converter. IEEE Journal of Solid-State Circuits August 1996, Vol. 31:1201-1207.
135. Huang Y. Design of high-performance switched-capacitor circuits in the presence of component imperfections. Ph.D. dissertation 1997, Oregon State University, New York.
136. Song B.-S., et al. A 12-b 1-Msample/s capacitor error-averaging pipelined A/D converter. IEEE Journal of Solid-State Circuits December 1988, Vol. SC-23:1324-1333.
137. Lee H.S., et al. A self-calibrating 15 bit CMOS A/D converter. IEEE Journal of Solid-State Circuits December 1984, Vol. SC-19:813-819.
138. Lin Y., Kim B., Gray P.R. A 13-b 2.5-MHz self-calibrated pipelined A/D converter in 3μm CMOS. IEEE Journal of Solid-State Circuits April 1991, Vol. 26:628-636.
139. Moon U., Silva J., Steensgaard J., Temes G.C. Switched-capacitor DAC with analogue mismatch correction. Electronics Letters October 1999, Vol. 35:1903-1904.
140. Razavi B., Wooley B.A. Design techniques for high-speed high-resolution comparators. IEEE Journal of Solid-State Circuits December 1992, Vol. SC-27:1916-1926.
141. van de Plassche R., Baltus P. An 8 b 100 MHz folding ADC. IEEE Solid-State Circuits Conference, Digest of Technical Papers February 1988, 222-223.
142. Kusumoto K., et al. A 10 b 20 MHz 30 mW pipelined interpolating CMOS ADC. IEEE Journal of Solid-State Circuits December 1993, Vol. 28:1200-1206.
143. Steyaert M., et al. A 100-MHz 8-bit CMOS interpolating A/D converter. IEEE Custom Integrated Circuits Conference May 1993, 28.1.1-28.1.4.
144. van de Grift R.E.J., et al. An 8-bit video ADC incorporating folding and interpolation techniques. IEEE Journal of Solid-State Circuits December 1987, Vol. SC-22:944-953.
145. Mehr I., Dalton D. A 500-MSamples/s, 6-b Nyquist-rate ADC for diskdrive read-channel application. IEEE Journal of Solid-State Circuits July 1999, Vol. 34:912-920.
146. Nagaraj K., et al. A dual-mode 700-Msamples/s 6-bit 200-MSamples/s 7-bit A/D converter in a 0.25μm digital CMOS process. IEEE Journal of Solid-State Circuits December 2000, Vol. 35:1760-1768.
147. Choi M., Abidi A.A. A 6-b 1.3-Gsamples/s A/D converter in 0.35μm CMOS. IEEE Journal of Solid-State Circuits December 2001, Vol. 36:1847-1858.
148. Jiang X., et al. A 2GS/s 6b ADC in 0.18 μm CMOS. IEEE Solid-State Circuits Conference, Digest of Technical Papers February 2003, 322-323.
149. Poulton K., et al. A 20GS/s 8 b ADC with a 1 MB memory in 0.18 μm CMOS. IEEE Solid-State Circuits Conference, Digest of Technical Papers February 2003, 318-319.
150. Taft R., et al. A 1.8 V 1.6GS/s 8 b self-calibrating folding ADC with 7.26 ENOB at Nyquist frequency. IEEE Solid-State Circuits Conference, Digest of Technical Papers February 2004, 252-253.
151. Shimizu T., et al. A 10-bit 20-MHz two-step parallel A/D converter with internal S/H. IEEE Journal of Solid-State Circuits February 1989, Vol. 24:13-20.
152. Wang Y., Razavi B. An 8-bit 150-MHz CMOS A/D converter. IEEE Journal of Solid-State Circuits March 2000, Vol. 35:308-317.
153. Limotyrakis S., et al. A 150-MS/s 8-b 71-mW CMOS time-interleaved ADC. IEEE Journal of Solid-State Circuits May 2005, Vol. 40:1057-1067.
154. Pan H., et al. A 3.3-V 12-b 50-MS/s A/D converter in 0.6μm CMOS with over 80-dB SFDR. IEEE Journal of Solid-State Circuits December 2000, Vol. 35:1769-1780.
155. Pan H., Abidi A.A. Spectral spurs due to quantization in Nyquist ADCs. IEEE Trans. on Circuits & Systems-I: Regular Papers August 2004, Vol. 51:1422-1439.
156. Lewis S.H., ray P.R. A pipelined 5-Msample/s 9-bit analog-to-digital onverter,". IEEE Journal of Solid-State Circuits December 1987, Vol. SC-22:954-961.
157. Karanicolas A.N., et al. A 15-b 1-Msample/s digitally self-calibrated pipelined ADC. IEEE Journal of Solid-State Circuits December 1993, Vol. 28:1207-1215.
158. Cline D. Noise, speed, and power trade-offs in pipelined analog-to-digital converters. Ph.D. dissertation 1995, UC Berkeley, Corvallis, OR.
159. Lee S., Song B.S. Digital-domain calibration of multi-step analog-to-digital converter. IEEE Journal of Solid-State Circuits December 1992, Vol. 27:1679-1688.
160. Murmann B., et al. A 12-b 75-MS/s pipelined ADC using open-loop residue amplification. IEEE Journal of Solid-State Circuits December 2003, Vol. 38:2040-2050.
161. Siragusa E., et al. A digitally enhanced 1.8 V 15 b 40Ms/s CMOS pipelined ADC. IEEE Solid-State Circuits Conference, Digest of Technical Papers February 2004, 452-453.
162. Liu H.C., et al. A 15-b 40-MS/s CMOS pipelined analog-to-digital converter with digital background calibration. IEEE Journal of Solid-State Circuits May 2005, Vol. 40:1047-1055.
163. Yang W., et al. A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquist input. IEEE Journal of Solid-State Circuits December 2001, Vol. 36:1931-1936.
164. Kitagawa A., et al. A 10 b 3MSamples/s CMOS cyclic ADC. IEEE Solid-State Circuits Conference, Digest of Technical Papers February 1995, 280-281.
165. McCreary J.L., et al. All-MOS charge redistribution A/D conversion technique-Part I. IEEE Journal of Solid-State Circuits December 1975, Vol. SC-10:371-379.
166. Temes G.C. Accurate linear data conversion using inaccurate nonlinear analog components. Research Seminar January 2003, Oregon State University, Berkeley, CA.
167. Enz C.C., Temes G.C. Circuit techniques for reducing the effects of opamp imperfections: autozeroing, correlated double sampling, and chopper stabilization. Proceedings of the IEEE November 1996, Vol. 84:1584-1614.
168. Robert J., et al. A 16-bit low-voltage CMOS A/D converters. IEEE Journal of Solid-State Circuits April 1987, Vol. SC-22:157-163.
169. Black W.C., et al. Time-interleaved converter arrays. IEEE Journal of Solid-State Circuits December 1980, Vol. SC-15:1022-1029.
170. Norsworthy S.R., Schreier R., Temes G.C. Delta-sigma data converters-Theory, design and simulation 1997, IEEE Press, Corvallis, OR.
171. Boser B.E., Wooley B.A. The design of sigma-delta modulation analog-to-digital converters. IEEE Journal of Solid-State Circuits December 1988, Vol. SC-23:1298-1308.
172. Silva J., et al. Wideband low-distortion delta-sigma ADC topology. Electronics Letters June 2001, Vol. 37:737-738.
173. Lee W.L. A novel higher order interpolative modulator topology for high resolution oversampling A/D converters. Master's thesis 1987, MIT, New York.
174. R. Schreier, Delta-sigma Toolbox in MATLAB, [Online]. Available at.
175. http://ftp.mathworks.com/pub/contrib/v5/control/delsig.
176. http://www.cisl.Columbia.edu/projects/switcap.
177. Schreier R. An empirical study of high-order single-bit delta-sigma modulators. IEEE Trans. on Circuits & Systems August 1993, Vol. 40(No. 8):461-466.
178. Sooch N.S., et al. 18-bit stereo D/A converter with integrated digital and analog filter. Proceedings of Ninth AES International Convention October 1991.
179. Ferguson P., et al. An 18b 20kHz dual sigma-delta A/D converter. IEEE Solid-State Circuits Conference, Digest of Technical Papers February 1991, 68-292.
180. Feldman A., et al. A 13-bit, 1.4-MS/s sigma-delta modulator for RF baseband channel applications. IEEE Journal of Solid-State Circuits October 1998, Vol. 33(No. 10):1462-1469.
181. Sun T. Compensation techniques for cascaded delta-sigma A/D converters and high-performance switched-capacitor circuits. Ph.D. dissertation 1998, Oregon State University, Cambridge, MA.
182. Abidi A. On the operation of cascode gain stages. IEEE Journal of Solid-State Circuits December 1988, Vol. 23(No. 6):1434-1437.
183. Carley L.R. A noise-shaping coder topology for 15+ bit converters. IEEE Journal of Solid-State Circuits April 1989, Vol. SC-24(No. 2):267-273.
184. Baird R.T., Fiez T.S. Linearity enhancement of multi-bit ΔΣ A/D and D/A converters using data weighted averaging. IEEE Trans. on Circuits & Systems December 19951, Vol. 42(No. 12):753-762.
185. Grilo J., et al. A 12-mW ADC delta-sigma modulator with 80 dB of dynamic range integrated in a single-chip blue-tooth transceiver. IEEE Journal of Solid-State Circuits March 2002, Vol. 37(No. 3):271-277.
186. Fujimori I., et al. A multibit delta-sigma audio DAC with 120-dB dynamic range. IEEE Journal of Solid-State Circuits August 2000, Vol. 35(No. 8):1066-1073.
187. Mohan N., et al. Power electronics converters, applications, and design 1995, John Wiley & Sons, Corvallis, OR. 2nd ed.
188. Yue C.P., Wong S.S. On-chip spiral inductors with patterned ground shields for Si-based RF Ics. IEEE Journal of Solid-State Circuits May 1998, Vol. 33(No. 5):743-752.
189. Nakagome Y., et al. An experimental 1.5-V 64 Mb DRAM. IEEE Journal of Solid-State Circuits April 1991, Vol. 26(No. 4):465-472.
190. Sawada K., Sugawara Y., Masui S. An on-chip high-voltage generator circuit for EEPROM's with a power supply voltage below 2 V. IEEE Symposium on VLSI Circuits, Digest of Technical Papers June 1995, 75-76.
191. Rohde U., Bucher T. Communication receivers: Principles and design 1988, McGraw-Hill, New York.
192. Dickson J. On-chip high-voltage generation in MNOS integrated circuits using an improved voltage multiplier technique. IEEE Journal of Solid-State Circuits June 1976, Vol. SC-11(No. 3):374-378.
193. Wu J., Chang Y., Chang K. 1.2 V CMOS switched-capacitor circuits. IEEE International Solid-State Circuits Conference, Digest of Technical Paperspp February 1996, 388-389.
194. Wu J., Chang K. MOS charge-pumps for low-voltage operation. IEEE Journal of Solid-State Circuits April 1998, Vol. 33(No. 4):592-597.
195. Johns D.A., Martin K. Analog integrated circuits design 1997, John Wiley & Sons, New York.
196. Lee S.C., et al. A low-ripple switched-capacitor DC-DC up converter for low-voltage applications. Proceedings of the 2nd IEEE Asia Pacific Conference on Integrated Circuits (ASIC) August 2000, 13-16.
197. Cho T., Gray P.R. A 10 b, 20 Msamples/s, 35 mW pipeline A/Dconverter. IEEE Journal of Solid-State Circuits March 1995, Vol. 30(No. 3):166-172.
198. Favrat P., Deval P., Declercq M. A high-efficiency CMOS voltage doubler. IEEE Journal of Solid-State Circuits March 1998, Vol. 33(No. 3):410-416.
199. van Steenwijk G., et al. Analysis and design of a charge-pump circuit for high output current applications. Proceedings of IEEE European Solid-State Circuits Conference September 1993, Vol. 3:118-121.
200. Maksimovic D., Dhar S. Switched-capacitor dc-dc converters for low-power on-chip applications. Proceedings of IEEE Power Electronics Specialist Conference August 1999, Vol. 1:54-59.
201. Ying T., Ki W.H., Chan M. Area-efficient CMOS charge-pumps for LCD drivers. IEEE Journal of Solid-State Circuits October 2003, Vol. 38(No. 10):1721-1725.
202. Wang C.-C., Wu J.-C. Efficiency improvement in charge-pump circuits. IEEE Journal of Solid-State Circuits April 1998, Vol. 32(No. 4):852-860.
203. Luo F., Ye H., Rashid M.H. Multiple-lift push-pull switched-capacitor Luo-converters. Proceedings of IEEE Power Electronics Specialist Conference June 2002, Vol. 2:415-420.
204. Lee J., et al. High-performance 1-Gb NAND flash memory with 0.12μm technology. IEEE Journal of Solid-State Circuits November 2002, Vol. 37(No. 11):1502-1509.
205. Harris W.S., Ngo K.D.T. Power switched-capacitor DC-DC converter: Analysis and design. IEEE Trans. on Aerospace and Electronic Systems April 1997, Vol. 33(No. 2):386-395.
206. Chang C., Knights M. Interleaving technique in distributed power conversion systems. IEEE Trans. on Circuit and Systems May 1995, Vol. 42(No. 5):245-251.
207. Chung H., Hui S., Tang S. Development of a multistage current-controlled switched-capacitor step-down DC-DC converter with continuous input current. IEEE Trans. on Circuit and Systems July 2000, Vol. 47(No. 7):1017-1026.
208. Hara N., Oota I., Ueno F. A new ring type switched-capacitor DC-DC converter with low inrush current and low ripple. Proceedings of IEEE Power Electronics Specialist Conference May 1998, Vol. 2:1536-1542.
209. Kotowski J., et al. Capacitor DC-DC converter with PFM and gain hopping April 2000, U.S. Patent 6055168.
210. Rao A., Mclntyre W., Moon U., Temes G.C. A noise-shaped switched-capacitor DC-DC voltage regulator. Proceedings of IEEE European Solid-State Circuits Conference September 2002, Vol. 2:375-378.
211. Semiconductor Industry Association, "International technology roadmap for semiconductors: 2002 update," [Online]. Available at.
212. http://www.sematech.org.
213. Baschirotto A., Castello R. A 1-V CMOS fully differential switched-opamp bandpass sigma-delta modulator. Proceedings of European Solid-State Circuits Conference (ESSCIRC) June 1997, Vol. 1:152-155.
214. Peluso V., Vancorenland P., Marques A.M., Steyaert M., Sansen W.C. A 900-mV low-power ΔΣ A/D converter with 77-dB dynamic range. IEEE Journal of Solid-State Circuits December 1998, Vol. 33(No. 12):1887-1897.
215. Waltari M., Halonen K. 1-V 9-Bit pipelined switched-opamp ADC. IEEE Journal of Solid-State Circuits January 2001, Vol. 36(No. 1):129-134.
216. Yao L., Steyaert M., Sansen W. A 0.8-V, 8μW, CMOS OTA with 50-dB gain and 1.2-MHz GBW in 18-pF load. Proceedings of European Solid-State Circuits Conference (ESSCIRC) June 2003, Vol. 2:297-300.
217. Rabii S., Wooley B.A. The design of low-voltage, low-power sigma-delta modulators 1999, Kluwer, New York.
218. Atachi T., et al. A 1.4 V switched capacitor filter. Proceedings of IEEE Custom Integrated Circuits Conference May 1990, Vol. 8:821-824.
219. Ramirez-Angulo J., Choi S., Altamirano G. Low voltage circuits building blocks using multiple input floating gate transistors. IEEE Trans. on Circuits and Systems-I November 1995, Vol. 42:971-974.
220. Blalock B., Allen P., Rincon-Mora G. Designing 1-V op amps using standard digital CMOS technology. IEEE Trans. on Circuits and Systems-II July 1998, Vol. 45:769-780.
221. Nakagome Y., et al. An experimental 1.5-V 64Mb DRAM. IEEE Journal of Solid-State Circuits April 1991, Vol. 26(No. 4):465-472.
222. Cho T., Gray P.R. A 10 b, 20 Msamples/s, 35 mW pipeline A/D converter. IEEE Journal of Solid-State Circuits March 1995, Vol. 30(No. 3):166-172.
223. Abo A., Gray P.R. A 1.5-V 10-bit 14.3-MS/s CMOS pipeline analog-to-digital converter. IEEE Journal of Solid-State Circuits May 1999, Vol. 34(No. 5):599-606.
224. Hu C. IC reliability simulation. IEEE Journal of Solid-State Circuits March 1992, Vol. 27(No. 3):241-246.
225. Dessouky M., Kaiser A. Very low-voltage digital-audio ΔΣ modulator with 88-dB dynamic range using local switch bootstrapping. IEEE Journal of Solid-State Circuits March 2001, Vol. 36(No. 3):349-355.
226. Steensgaard J. Bootstrapped low-voltage analog switches. Proceedings of IEEE International Symposium on Circuits and Systems May 1999, Vol. 2:29-32.
227. Pan H., et al. A 3.3-V 12-b 50-MS/s A/D converter in 0.6μm CMOS with over 80-dB SFDR. IEEE Journal of Solid-State Circuits December 2000, Vol. 35:1769-1780.
228. Crols J., Steyaert M. Switched-opamp: An approach to realize full CMOS switched-capacitor circuits at very low power supply voltages. IEEE Journal of Solid-State Circuits August 1994, Vol. 29(No. 8):924-936.
229. Bidari E., Keskin M., Maloberti F., Moon U., Steensgaard J., Temes G.C. Low-voltage switched-capacitor circuits. Proceedings of IEEE International Symposium on Circuits and Systems May 2000, Vol. V:445-448.
230. Baschirotto A., Castello R. A 1-V 1.8-MHz CMOS switched-opamp SC filter with rail-to-rail output swing. IEEE Journal of Solid-State Circuits December 1997, Vol. 32:1979-1986.
231. Cheung V.S.-L., Luong H.C., Ki W.-H. A 1-V CMOS switched-opamp switched-capacitor pseudo-2-path filter. IEEE Journal of Solid-State Circuits January 2001, Vol. 36:14-22.
232. Cheung V.S.-L., Luong H.C., Ki W.-H. A 1-V 10.7-MHz switched-opamp bandpass ΣΔ modulator using double-sampling finite-gain-compensation techniques. IEEE Journal of Solid-State Circuits October 2002, Vol. 37:1215-1225.
233. Temes G.C. Finite amplifier gain and bandwidth effect in switched-capacitor filters. IEEE Journal of Solid-State Circuits June 1980, Vol. SC-15:358-361.
234. Martin K., Sedra A.S. Effects of the op amp finite gain and bandwidth on the performance of switched-capacitor filters. IEEE Trans. Circuits and Systems August 1981, Vol. CAS-28:822-829.
235. Temes G.C. Autozeroing and correlated double sampling techniques. Research Seminar May 2002, Oregon State University, Norwood, MA.
236. Razavi B., Wooley B.A. Design techniques for high-speed, high-resolution comparators. IEEE Journal of Solid-State Circuits December 1992, Vol. 27:1916-1926.
237. Krummenacher F. Micropower switched capacitor biquadratic cell. IEEE Journal of Solid-State Circuits June 1982, Vol. SC-17(No. 3):507-512.
238. Gregorian R. High-resolution switched-capacitor D/A converter. Microelectronic Journal 1981, (No. 12):10-13.
239. Enz C.C., Temes G.C. Circuit techniques for reducing the effects of opamp imperfections: Autozeroing, correlated double sampling, and chopper stabilization. Proceedings of the IEEE November 1996, Vol. 84:1584-1614.
240. Haug K., Temes G.C., Martin K. Improved offset-compensation schemes for SC circuits. Proceedings of IEEE International Symposium on Circuits and Systems May 1984, Vol. 3:1054-1057. Montreal, Canada.
241. Martin K. A differential switched-capacitor amplifier. IEEE Journal of Solid-State Circuits February 1987, Vol. SC-22(No. 1):104-106.
242. Larson L.E., Temes G.C. SC building blocks with reduced sensitivity to finite amplifier gain, bandwidth and offset voltage. Proceedings of IEEE International Symposium on Circuits and Systems May 1987, Vol. 1:334-338.
243. Nagaraj K. Switched-capacitor circuits with reduced sensitivity to amplifier gain. IEEE Trans. Circuits and Systems May 1987, Vol. CAS-34(No. 5):571-574.
244. Yoshizawa H., Huang Y., Temes G.C. Improved SC amplifiers with low sensitivity to op-amp imperfections. Electron. Letters February 1997, Vol. 33(No. 5):348-349.
245. Liu M. The design of delta-sigma modulators for multi-standard RF receivers. master's thesis June 2003, Oregon State University, Philadelphia, PA.
246. Gray P.R., Meyer R. Future directions of silicon ICs for RF personal communications. Proceedings of the IEEE Custom Integrated Circuits Conference May 1995, 83-90.
247. Koullias I.A., et al. A 900-MHz transceiver chip set for dual-mode cellular radio mobile terminals. IEEE Solid-State Circuits Conference, Digest of Technical Papers February 1993, 140-141.
248. Abidi A.A. The future of CMOS wireless transceivers. IEEE Solid-State Circuits Conference, Digest of Technical Papers February 1997, 118-119.
249. Rudell J.C., et al. Recent developments in high integration multi-standard CMOS transceivers for personal communication systems. IEEE Proceedings of International Symposium for Low-Power Electronics and Devices August 1998, 149-154.
250. van Veldhoven R., et al. A 3.3-mW ΣΔ modulator for UMTS in 0.18μm CMOS with 70-dB dynamic range in 2-MHz bandwidth. IEEE Journal of Solid-State Circuits December 2002, Vol. 37:1645-1652.
251. Li X., Ismail M. Multi-standard CMOS wireless receivers: Analysis and design 2002, Kluwer Academic Publishers, Corvallis, OR.
252. Siragusa E., et al. A digitally enhanced 1.8 V 15 b 40Ms/s CMOS pipelined ADC. IEEE Solid-State Circuits Conference, Digest of Technical Papers February 2004, 452-453.
253. Liu H.C., et al. A 15-b 40-MS/s CMOS pipelined analog-to-digital converter with digital background calibration. IEEE Journal of Solid-State Circuits May 2005, Vol. 40:1047-1055.
254. Feldman A. A 13-bit, 1.4-MS/s, 3.3-V sigma-delta modulator for RF baseband channel applications. Proceedings of the IEEE Custom Integrated Circuits Conference May 1998, 229-232.
255. Piazza F., et al. A 0.25 mm CMOS transceiver front-end for GSM. Proceedings of the IEEE Custom Integrated Circuits Conference May 1998, 413-416.
256. Rohde U., Bucher T. Communication receivers: Principles and design 1988, McGraw-Hill, Berlin, Germany.
257. Razavi B. RF Microelectronics 1998, Prentice-Hall, New York.
258. Abidi A.A. Direct-conversion radio transceiver for digital communications. IEEE Journal of Solid-State Circuits December 1995, Vol. 30:1399-1410.
259. Longo L., et al. A cellular analog front with a 98-dB IF receiver. IEEE Solid-State Circuits Conference, Digest of Technical Papers February 1993, 36-37.
260. Hairapetian A. A 81-MHz IF receiver in CMOS. IEEE Solid-State Circuits Conference, Digest of Technical Papers February 1996, 56-57.
261. Burger T., Huang Q. A 13.5-mW 185-Msample/s ΔΣ modulator for UMTS/ GSM dual-standard IF reception. IEEE Solid-State Circuits Conference, Digest of Technical Papers February 2001, 44-45.
262. Breems L.J., et al. A 1.8-mW CMOS sigma-delta modulator with integrated mixer for A/D conversion of IF signals. IEEE Journal of Solid-State Circuits April 2000, Vol. 35:468-475.
263. Breems L.J., et al. A quadrature data-dependent DEM algorithm to improve image rejection of a complex AS modulator. IEEE Journal of Solid-State Circuits December 2001, Vol. 36:1879-1886.
264. Tabatabaei A. A two-path bandpass sigma-delta modulator with extended noise shaping. IEEE Journal of Solid-State Circuits December 2000, Vol. 35:1799-1809.
265. Schreier R., et al. A 10-300-MHz IF-digitizing IC with 90-105-dB dynamic range and 15-333-kHz bandwidth. IEEE Journal of Solid-State Circuits December 2002, Vol. 37:1636-1644.
266. Norsworthy S.R., Schreier R., Temes G.C. Delta-sigma data converters:Theory, design and simulation 1997, IEEE Press, Upper Saddle River, NJ.
267. Jantzi S. A fourth-order bandpass sigma-delta modulator. IEEE Journal of Solid-State Circuits March 1993, Vol. 28:282-291.
268. ETS 300 577-579, GSM: Digital cellular telecommunications systems 1997, ETSI, New York.
269. EN 300 176-1 Vl.3.2, DECT: Approval test specification; Part 1: Radio 1999, ETSI.
270. Third Generation Partnership Project. [Online]. Available at.
271. http://www.3gpp.org.
272. van der Zwan E.J., et al. A 10.7-MHz IF-to-baseband sigma-delta A/Dconversion system for AM/FM radio receivers. IEEE Journal of Solid-State Circuits December 2000, Vol. 35:1810-1819.
273. Quinn P.J. A 10.7-MHz CMOS SC IF filter using orthogonal hardware modulation. IEEE Journal of Solid-State Circuits December 2000, Vol. 35:1865-1876.
274. Gregorian R., Temes G.C. Analog MOS integrated circuits for signal processing 1986, John Wiley & Sons.
275. Sansen W. Transient analysis of charge transfer in SC filters-gain error and distortion. IEEE Journal of Solid-State Circuits February 1987, Vol. 22:268-276.
276. William L.A. Modeling and design of high-resolution sigma-delta modulators. Ph.D. dissertation 1993, Stanford University, New York.
277. Brooks T. A cascaded sigma-delta pipelined A/D converter with 1.25 MHz signal bandwidth and 89 dB SNR. IEEE Journal of Solid-StateCircuits July 1997, Vol. 32:1896-1906.
278. Hsieh K., et al. A low-noise chopper stabilized switched-capacitor filtering technique. IEEE Journal of Solid-State Circuits December 1981, Vol. SC-16:708-715.
279. Geerts Y., et al. A 3.3-V, 15-bit, delta-sigma ADC with a signal bandwidth of 1.1 MHz for ADSL applications. IEEE Journal of Solid-State Circuits July 1999, Vol. 34:927-936.
280. Martin K., et al. A differential switched-capacitor amplifier. IEEE Journal of Solid-State Circuits February 1987, Vol. SC-22:104-106.
281. Bult K., Geelen G. A fast-settling CMOS op amp for SC circuits with 90-dB DC gain. IEEE Journal of Solid-State Circuits December 1990, Vol. 25:1379-1383.
282. Razavi B. Design of analog CMOS integrated circuits 2001, McGraw-Hill, Palo Alto, CA.
283. Sooch N., AT&T Bell Lab. MOS cascode current mirror 1985, U.S. Patent 4550284.
284. Cho T., et al. A 10b, 20Msample/s, 35mW pipelined analog-to-digital converter. IEEE Journal of Solid-State Circuits March 1995, Vol. 30:166-172.