Minplex - A compactor that minimizes the bounding rectangle and individual rectangles in a layout

Proceedings - Design Automation Conference

Volumn , Issue , 1986, Pages 123-130

  Lin, Selling L ^a   Allen, Jonathan ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; DIRECTED GRAPHS; GRAPH THEORY; LINEAR PROGRAMMING;

CONSTRAINT GRAPH; GRAPH-THEORETIC; MINIMIZATION ALGORITHMS; MINIMIZATION PROBLEMS; SIMPLEX METHODS; TWO-STAGE PROCESS; WEIGHTED SUM; WIRELENGTH MINIMIZATION;

GEOMETRY;

EID: 85013582474     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DAC.1986.1586078     Document Type: Conference Paper

References (18)

1. W. Wolf, "Two-Dimensional Compaction Strategies," Ph.D. Thesis, Stanford University, 1984.
2. M. Schlag, Y.Z. Liao and C.K. Wong, "An Algorithm for Optimal Two Dimensional Compaction of VLSI Layouts," Integration, 1983, pp.179 - 209.
3. A.E. Dunlop, "SLIM - The Translation of Symbolic Layouts into Mask Data," Proc. of the 17th Design Automation Conference, IEEE (1980), 595-602
4. A.E. Dunlop, "SLIP: Symbolic Layout of Integrated Circuits with Compaction," Computer Aided Design, November 1978.
5. N. Weste, "Virtual Grid Symbolic Layout," Proceedings of the 18th Design Automation Conference, June 1981, pp. 225 - 233.
6. D.G. Boyer and N. Weste, "Virtual Grid Compaction Using the Most Recent Layers Algorithm," Proceedings of the ICCAD, June 1983.
7. M.Y. Hsueh, "Symbolic Layout and Compaction of Integrated Circuits," Ph.D. thesis, EBCS division, University of California, Berkeley, CA, (1979).
8. R.A, Auerbach, B.VV. Lin, E.A. Elsayed, "Layout Aid for the Design of VLSI Circuits," computer Aided design 15, 5 (1981), 271-276.
9. G. Kedem, H. Watanabe, "Optimization Techniques for IC Layout and Compaction," TR 117, Dep. of Comp. Sci., University of Rochester Rochester N.Y. (19812).
10. W.L. Schiele, "Improved Compaction by Minimized Length of Wires," Proceedings of the 20th Design Automation Conference, June 1983, pp. 121 - 127.
11. W. Wolf, "An Experimental Comparison of 1-D Compaction Algorithms," 1985 Chapel Hill Conference on VLSI, pp. 105 - 180.
12. Y.E. Chow, "A Subjective Review of Compaction," Proceedings of the 22nd Design Automation Conference, June 1985, pp. 396 - 404.
13. R. Mathews, J. Newkirk, and P. Eichenberger, "A Target Language for Silicon Compilers," Compcon Proceedings, pp. 349 - 353, Spring 1982.
14. E. Lawler, Combinatory Optimization: Networks and Matriods, Halt, Hinehart and Winston. New York, 1976.
15. F. Ficken, The Simplex Method of Linear Programing, Halt, Rinehart and Winston. New York, 1961.
16. M.I. Shamos, "Computational Geometry," Ph.D. dissertation. Yale University, 1977
17. L. Guibas and J. Saxe Problem 80 - 15, Journal of Algorithms, Vol. 4, pp. 177 - 181, 1983.
18. B. Liskov, R. Atkinson, T. Bloom, E. Moss, C. Schaffert, B. Scheifler, A. Snyder, CLU Reference Manual, Springer-Verlag, 1981