Bipolar circuit scaling

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 1979, Pages 86-87

  Solomon, P ^a   Tang, D ^a  

^a IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR INTEGRATED CIRCUITS; TIMING CIRCUITS;

BIPOLAR CIRCUITS; DOPING LEVELS; EMITTER COUPLED LOGIC; PHYSICAL LIMITATIONS; SCALING PRINCIPLE;

COMPUTER CIRCUITS;

EID: 85012796392     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.1979.1155913     Document Type: Conference Paper

References (3)

1. Dennard, R. H., Gaensslen, F. H., Kuhn, L., Yu, H. N., "Design of Micron MOS Switching Devices", IEDM Digest Technical Papers, p. 168-170; 1972.
2. Hoeneissen, B., Mead, C. A., "Limitations in Microelec-tronics-II. Bipolar Technology", Solid-State Electronics, vol. 15, p. 891-897; 1972.
3. Tang, D. D., Solomon, P. M., "Bipolar Transistor Design for Optimized Power-Delay Logic Circuits"; submitted to JSSC for publication.